Cirrus Logic EP93 Series User Manual page 589

0:
UART3HDLCCtrl
31 30 29 28
RSVD
15 14 13 12
FLAG
Address:
0x808E_020C - Read/Write
Default:
0x0000_0000
Definition:
HDLC Control Register
Bit Descriptions:
RSVD:
CMAS:
TXCM:
RXCM:
TXENC:
DS785UM1
Must be written as "0".
27 26 25 24
CMAS TXCM RXCM TXENC
11 10 9 8
CRCN CRCApd IDLE AME
Reserved. Unknown During Read.
Clock Master:
1 - Transmitter and/or receiver use 1x clock generated by
the internal transmitter.
0 - Transmitter and/or receiver use 1x clock generated
externally.
Transmit Clock Mode.
1 - Generate 1x clock when in synchronous HDLC mode
using NRZ encoding.
0 - Do not generate clock.
This bit has no effect unless TXENC is clear and
synchronous HDLC is enabled.
Receive Clock Mode.
1 - Use external 1x clock when in synchronous HDLC
mode using NRZ encoding.
0 - Do not use external clock.
This bit has no effect unless RXENC is clear and
synchronous HDLC is enabled.
Transmit Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled
Copyright 2007 Cirrus Logic
23 22 21 20
RXENC SYNC TFCEN TABEN
7 6 5 4
RSVD RXE
UART3 With HDLC Encoder
EP93xx User's Guide
19 18 17 16
RFCEN RILEN RFLEN RTOEN
3 2 1 0
TXE TUS CRCE CRCS
16-13
16