Table 13-6. Sync Memory Cas; Table 13-7. Sync Memory Ras, Burst Type, And Write Burst Length; Table 13-8. Burst Length - Cirrus Logic EP93 Series User Manual

Note: "RFU" means Reserved for Future Use.
Table 13-6, Table
Length, respectively.
CAS Value
000
001
010
011
100
101
110
111

Table 13-7. Sync Memory RAS, Burst Type, and Write Burst Length

Value
RAS = 0
RAS = 1
BT = 0
BT = 1
WBM = 0
WBM = 1
Burst Length
000
001
010
011
100
101
110
111
When using a 32-bit wide external memory bus, the following Read addresses must be used
to set up the specified parameters, where H can be 0x0, 0xC, 0xD, 0xE or 0xF as shown in
Table 13-2:
• SDRAM default READ Address: 0xH000_C800 — sets WBM=0, TM=0, CAS=3,
Sequential, BL=4
• SFLASH default READ Address: 0xH008_C800 — sets WBM=1, TM=0, CAS=3,
Sequential, BL=4
• SROM default READ Address: 0xH001_8400 — sets RAS=2, CAS=5, Sequential, BL=4
DS785UM1
13-7, and Table 13-8 show the bit field values for CASL, RAS, and Burst

Table 13-6. Sync Memory CAS

SDRAM
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
SDRAM
Not applicable
Not applicable
Sequential
Interleaved
Use BL value
Write Burst = 1

Table 13-8. Burst Length

SDRAM
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User's Guide
SFLASH SROM
Reserved Reserved
1 2
2 3
3 4
Reserved 5
Reserved 6
Reserved 7
Reserved 8
SFLASH SROM
Not applicable 1 clk
Not applicable 2 clk
Sequential Sequential
Interleaved Interleaved
Use BL value Use BL value
Write Burst = 1 Not applicable
SFLASH SROM
1 Reserved
2
4
8 Reserved
Reserved
Reserved
Reserved
Reserved
13
4
8
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13-7