Error Bits; Disabling The Fifos; System/Diagnostic Loopback Testing; Uart Character Frame - Cirrus Logic EP93 Series User Manual

UART1 With HDLC and Modem Control Signals
EP93xx User's Guide

14.2.2.1 Error Bits

Three error bits are stored in bits [10:8] of the receive FIFO, and are associated with a
particular character. See
error but it is not associated with a particular character in the receive FIFO. The overrun error
is set when the FIFO is full and the next character has been completely received in the shift
register. The data in the shift register is overwritten but it is not written into the FIFO.
14

14.2.2.2 Disabling the FIFOs

Additionally, it is possible to disable the FIFOs. In this case, the transmit and receive sides of
the UART have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set
when a word has been received and the previous one was not yet read. In this
implementation, the FIFOs are not physically disabled, but the flags are manipulated to give
the illusion of a 1-byte register.

14.2.2.3 System/diagnostic Loopback Testing

It is possible to perform loopback testing for UART data by setting the Loop Back Enable
(LBE) bit to 1 in the control register UARTxCtrl (bit 7).
Data transmitted on UARTTXD output will be received on the UARTRXD input.

14.2.2.4 UART Character Frame

The UART character frame is shown in
14-6
Table 14-1. There is an additional error which indicates an overrun

Table 14-1. Receive FIFO Bit Functions

FIFO bit
10
9
8
7:0

Figure 14-2. UART Character Frame

Figure 14-3. UART Character Frame

Copyright 2007 Cirrus Logic
Function
Break error
Parity error
Framing error
Received data
Figure 14-2:
DS785UM1