Cirrus Logic EP93 Series User Manual page 654

Real Time Clock With Software Trim
EP93xx User's Guide
RTCLoad
31 30
15 14
20
Address:
Default:
Definition:
Bit Descriptions:
RTCCtrl
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
20-6
29 28 27 26
13 12 11 10
0x8092_000C - Read/Write
0x0000_0000
RTC Load Register. Contains the 32 bit load value. Data written to this register
is transferred to the RTCData on the next 1 Hz tick.
RTCLR:
29 28 27 26
13 12 11 10
0x8092_0010 - Read/Write
0x0000_0000
RTC Interrupt Control Register. Contains the interrupt enable control bit.
RSVD:
MIE:
Copyright 2007 Cirrus Logic
25 24 23 22
RTCLR
9 8 7 6
RTCLR
Load value.
25 24 23 22
RSVD
9 8 7 6
RSVD
Reserved, unknown during read.
Match Interrupt Enable,
1 - RTC match interrupt is enabled
0 - interrupt disabled.
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
MIE
DS785UM1