Cirrus Logic EP93 Series User Manual page 211

Arm 9 embedded processor family
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Vertical
down
counter
VSYNCn
VACTIVE
VBLANKn
SPCLK
DURING
Vertical
HCLKSTOTAL
Horizontal
down
0h
counter
HSYNCn
Horizontal Back
HACTIVE
HBLANKn
SPCLK
DURING
Horizontal
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
0h
VLINESTOTAL
VLINESTOTAL -1
Vertical Sync
Interval
LINECARRY (CLKS)
HCLKSTOTAL -1
HSYNCSTART
HSYNCSTOP
Horizontal Active
Porch
Figure 7-9. Progressive/Dual Scan Video Signals
Copyright 2007 Cirrus Logic
VLINESTOTAL
VSYNCSTART
VSYNCSTOP
VCLKSTOP
VCLKSTART
VACTIVESTRT
VACTIVESTOP
Vertical Back Porch
Vertical Active
Video
VBLANKSTRT
VBLANKSTOP
HCLKSTOTAL
1h
0h
HCLKSTOP
HCLKSTART
HACTIVESTRT
HACTIVESTOP
Video
Horizontal Front
Porch
HBLANKSTRT
HBLANKSTOP
EP93xx User's Guide
1h
0h
VLINESTOTAL
Vertical Front
Porch
7
7-29

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Ep9315Ep9301Ep9302Ep9307Ep9312

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