Figure 9-2. Ethernet Frame / Packet Format (Type Ii Only) - Cirrus Logic EP93 Series User Manual

Arm 9 embedded processor family
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1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
9
alternating 1s / 0s
D ire c tio n o f T ra n s m is sio n
In the receiver, the MAC detects the preamble and locks onto the embedded clock. The MAC
performs destination address filtering (individual, group, broadcast, promiscuous) on the DA.
The MAC engine computes the correct FCS, and reports if the received FCS is "good" or
"bad". The data after the SFD and before the FCS is supplied to the host as the received
data. The received FCS may also be passed to the host by setting RXCtl.BCRC.
9-4
E th e rn e t F ra m e /P a c k e t F o rm a t (T y p e II, o n ly )
up to 7 bytes
1 byte
6 bytes
S F D
D A
p re am b le
S F D = S ta rt o f F ra m e D e lim ite r
D A = D e s tin a tio n A d d re s s
S A = S o u rc e A d d re ss
L L C = L o gic a l L in k C o n tro l
F C S = F ra m e C h e c k S e q u e n c e (s o m etim e s
c a lle d C y c lic R e d u nd a n c y C h e c k , o r C R C )

Figure 9-2. Ethernet Frame / Packet Format (Type II only)

Copyright 2007 Cirrus Logic
Packet
F ra m e
6 bytes
2 bytes
SA
optional field
fra m e le n g th
m in 6 4 b y te s
m a x 1 5 1 8 b yte s
T he o ptio n a l fie ld , w h ic h is tw o by te s
lon g, is eith er a T Y P E field fo r E th e rne t
a pp lic atio n s ,o r is a L E N G T H fie ld for
IE E E 80 2.3 a pplic atio n s .
T he P ad fie ld w ill b e u s e d o nly to ge t
th e fra m e to th e m inim u m s ize .
S e e p a ra g ra p h 6 .3 .3.
W he n th e C S 8 93 1 ad d s p ad b y tes ,
th e p ad is the la st b yte of th e
L LC da ta fie ld re p ea te d M tim es .
N bytes
M bytes
4 bytes
LL C da ta
Pad
F C S
DS785UM1

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