Table 5-7. Audio Interfaces Pin Assignment - Cirrus Logic EP93 Series User Manual

System Controller
EP93xx User's Guide
5
Note: The I
Note: The I
5-26
I2SonAC97:
2
S should be enabled on only one set of pins. Therefore I2SonAc97 and I2SonSSP
are mutually exclusive. Setting both I2SonAc97 and I2SonSSP will cause unexpected
behavior.
I2SonSSP:
2
S should be enabled on only one set of pins. Therefore I2SonAc97 and I2SonSSP
are mutually exclusive. Setting both I2SonAc97 and I2SonSSP will cause unexpected
behavior.

Table 5-7. Audio Interfaces Pin Assignment

Normal Mode
Pin
Name
Description
SCLK1 SPI Bit Clock
SFRM1 SPI Frame Clock
SSPRX1 SPI Serial Input
SSPTX1 SPI Serial Output
ARSTn AC'97 Reset
ABITCLK AC'97 Bit Clock
AC'97 Frame
ASYNC
AC'97 Serial
ASDI
AC'97 Serial
ASDO
EonIDE:
PonG:
GonIDE:
HonIDE:
Copyright 2007 Cirrus Logic
2
Audio - I S on AC97 pins. The I
pins. See Audio Interface pin assignments in
2
Audio - I S on SSP pins. The I
MCLK is not available in this pin option. See Audio
Interface pin assignments in
2
I S on SSP
Mode
Pin
Pin Description
2
I S Serial Clock
2
I S Frame Clock
2
I S Serial Input
2
I S Serial Output
2
(No I S Master
Clock)
AC'97 Reset
AC'97 Bit Clock
AC'97 Frame Clock
Clock
AC'97 Serial Input
Input
AC'97 Serial Output
Output
GPIO Port E on IDE pins:
0 - GPIO Port E used for IDE
1 - GPIO Port E used for GPIO
PWM 1 output on EGPIO pin
GPIO Port G on IDE pins
0 - GPIO Port G used for IDE
1 - GPIO Port G used for GPIO
GPIO Port H on IDE pins
2
S block uses the AC97
Table
2
S block uses the SSP pins.
Table 5-7.
2
I S on AC'97
Mode
Pin Description
SPI Bit Clock
SPI Frame Clock
SPI Serial Input
SPI Serial Output
2
I S Master Clock
2
I S Serial Clock
2
I S Frame Clock
2
I S Serial Input
2
I S Serial Output
DS785UM1
5-7.