Cirrus Logic EP93 Series User Manual page 417

ABORT:
ICE:
PPALLOC
31 30 29 28
15 14 13 12
Address:
Channel Base Address + 0x0008 - Read/Write
Definition:
This is the Peripheral Port Allocation register used to configure the internal
M2P channel programmability. It is possible to program a channels use on one
of a number of different peripherals.
There can be 20 external peripherals - 10 Tx and 10 Rx - connected to the 20
"ports" of the DMA. The 10 internal M2P DMA channels can serve 10 of these
ports at one time.
Bit Descriptions:
RSVD:
Note: PPALLOC:Table
allocation for both a transmit channel and a receive channel.
Two channels cannot be programmed to serve the same port since, in the case of an
erroneous software write operation, the lower channel number is given priority. For
example, if software writes the value 0x01 to Channel 0 Tx PPALLOC[3:0], and also writes
this same value to Channel 2 Tx PPALLOC[3:0], then the Channel 0 Tx will be configured
for Port 0 and Channel 2 will not function correctly.
The PPALLOC register must be written to before a channel is enabled. If this is not done,
then the default allocation of the ports will be used.
DS785UM1
This bit determines how the DMA Channel State machine
behaves while in the NEXT state and in receipt of a
peripheral error, indicated on RxEnd/TxEnd. This bit is
ignored when ICE is set.
0 - NEXT -> ON state, effectively ignoring the error.
1 - NEXT -> STALL state, effectively disabling the channel.
No STALLInt interrupt is set for this condition.
Ignore Channel Error bit. Setting this bit results in
suppression of the generation of the ChErrorInt interrupt
and does not result in buffer termination. This bit may be
set for data streams whereby the end user is tolerant to
occasional bit errors.
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
10-5, Table 10-6, and Table 10-7
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
give the PPALLOC decode for the port
DMA Controller
EP93xx User's Guide
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3 2 1 0
PPALLOC
10-23
10