Cirrus Logic EP93 Series User Manual page 730

Synchronous Serial Port
EP93xx User's Guide
SSPCPSR
31 30
15 14
23
Address:
Default:
Definition:
Bit Descriptions:
SSPIIR / SSPICR
31 30
15 14
Address:
Note: A write to this register clears the receive overrun interrupt, regardless of the data value
Default:
23-18
29 28 27 26
13 12 11 10
RSVD
0x808A_0010 - Read/Write
0x0000_0000
SSPCPSR is the clock prescale register and specifies the division factor by
which the input SSPCLK should be internally divided before further use.
The value programmed into this register should be an even number between 2
and 254. The least significant bit of the programmed number is hard-coded to
zero. If an odd number is written to this register, data read back from this
register will have the least significant bit as zero.
RSVD:
CPSDVSR:
29 28 27 26
13 12 11 10
0x808A_0014 - Read Only
written.
0x0000_0000
25 24 23 22
RSVD
9 8 7 6
Reserved. Unknown During Read.
Clock pre-scale divisor. Should be an even number from 2
to 254, depending on the frequency of SSPCLK. The least
significant bit CPSDVSR[0] always returns zero on reads
since it is hard-coded to 0
25 24 23 22
RSVD
9 8 7 6
RSVD
Copyright 2007 Cirrus Logic
21 20 19 18
5 4 3 2
CPSDVSR
21 20 19 18
5 4 3 2
RORIS
17 16
1 0
17 16
1 0
TIS RIS
DS785UM1