Cirrus Logic EP93 Series User Manual page 370

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
9
9-68
MT: Manual Transfer. Writing a one to this bit causes all
internal FIFOs to be marked pending for transfer, as if they
had crossed their threshold. This provides a mechanism
for flushing stale status from the internal FIFOs, when the
Timed Transfer is not used and non zero thresholds have
been set. When the Manual Transfer is set, the Transfer
Pending (BMCtl), is set until all FIFOs have been either
active for a DMA transfer, or have been determined
inactive (that is, an empty receive data FIFO). When
reading the BMCtl register, the Manual Transfer bit will
always return a zero.
TT: Timed Transfer. Setting the Timed Transfer bit causes the
internal FIFOs to be marked as pending for transfer
whenever the timer reaches zero. This provides a
mechanism for flushing stale status from the internal
FIFOs when a non zero threshold has been set.
UnH: Underrun Halt. When set, this bit causes the transmit
descriptor to perform the following operations when a
transmit underrun is encountered:
1. Halt all transmit DMA operations.
2..Flush the transmit descriptor queue.
3.Set transmit enqueue to zero.
TxChR: Transmit Channel Reset. Writing a "1" to Transmit Channel
Reset causes the Transmit Descriptor Processor and the
transmit FIFO to be reset. This bit is an act-once-bit and
will clear automatically when the reset is complete.
TxDis: Transmit Disable. Writing a "1" to Transmit Disable causes
the transmit DMA transfers to be halted. If a transmit frame
is currently in progress, transfers are halted when the
transmit status is written to the status buffer. When
transfers have been halted, the TxAct bit (Bus Master
Status) is clear. TxDis is an act-once-bit and will clear
immediately.
Copyright 2007 Cirrus Logic
This allows the host to re-initialize the Transmit
Descriptor Processor, to start at the desired point.
When clear, the MAC will proceed to the next
transmit frame in the queue.
DS785UM1