Compare Instructions - Cirrus Logic EP93 Series User Manual

MaverickCrunch Co-Processor
EP93xx User's Guide
31:28 27:24
3
cond 1 1 1 0
Definition:
Mnemonic:
Bit Definitions:
31:28 27:24
cond 1 1 1 0
Definition:
Mnemonic:
Bit Definitions:

3.5.6 Compare Instructions

31:28
cond 1 1 1 0
Definition:
3-36
Shift 32-bit Integer Immediate
23:22 21:20
0 0 0 0
Shift a 32-bit integer by the count specified in the seven bit, two's complement
immediate value. A positive number indicates a left shift and a negative
number indicates a right shift. This instruction may also be used to copy a 32-
bit integer from one register to another using a shift value of 0.
CFSH32<cond> CRd, CRn, Shift[6:0]
CRd:
CRn:
Shift[6:0]:
Shift 64-bit Integer Immediate
23:22 21:20
0 0 1 0
Shifts a 64-bit integer by a count specifies in the seven bit, two's complement
immediate value. A positive number indicates a left shift and a negative
number indicates a right shift. This instruction may also be used to copy a 64-
bit integer from one register to another by using a shift value of 0.
CFSH64<cond> CRd, CRn, Shift[6:0]
CRd:
CRn:
Shift[6:0]:
Compare Single Precision Floating Point
27:24 23:22 21
0 0 0
Compares two single precision floating point numbers and stores an integer
representing the result in the ARM920T register; the highest four bits of the
integer result match the N, Z, C, and V bits, respectively, in the ARM920T's
program status register, while the bottom 28 bits are zeros. If Rd = 15, then the
four status bits are stored in the ARM status register, CPSR.
19:16 15:12
CRn CRd
Destination register
Source register
Shift count.
19:16 15:12
CRn CRd
Destination register
Source register
Shift count.
20 19:16 15:12
1 CRn Rd
Copyright 2007 Cirrus Logic
11:8 7:5
0 1 0 1 Shift[6:4]
11:8 7:5
0 1 0 1 Shift[6:4]
11:8 7:5
0 1 0 0 1 0 0
4 3:0
0 Shift[3:0]
4 3:0
0 Shift[3:0]
4 3:0
1 CRm
DS785UM1