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103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features
Multi-bit Delta–Sigma Modulator
103 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
–
± 12 dB Gain, 0.5-dB Step Size
–
Zero-crossing, Click-free Transitions
Stereo Microphone Inputs
–
+32 dB Gain Stage
–
Low-noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable 24-bit, Left-justified or I²S Serial
Audio Interface Formats
System Features
Power-down Mode
+5 V Analog Power Supply, Nominal
+3.3 V Digital Power Supply, Nominal
Direct Interface with 3.3 V to 5 V Logic Levels
Pin Compatible with CS5345 (*See
for details.)
3.3 V to 5 V
I²C
/SPI
Control Data
Interrupt
Overflow
Reset
Serial
Audio
Output
Preliminary Product Information
http://www.cirrus.com
Section 2
3.3 V
Register Configuration
High Pass
Low-Latency
Filter
Anti-Alias Filter
High Pass
Low-Latency
Filter
Anti-Alias Filter
This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
General Description
The CS5346 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5346 performs stereo analog-to-digi-
tal (A/D) conve rsion of 24-bit serial values at sa mple
rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of ±12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta-sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 8 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5346 and other devices operating over a
wide range of logic levels.
The CS5346 is available in a 48-pin LQFP package in
Commercial (-40° to +85° C) grade. The CDB5346 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to
"Ordering Information" on page 38
details.
5 V
Internal Voltage
Reference
Multibit
Oversampling
PGA
ADC
Multibit
PGAA
Oversampling
ADC
CS5346
for complete
Left PGA Output
Right PGA Output
Stereo Input 1
Stereo Input 2
Stereo Input 3
+32 dB
MUX
Stereo Input 4 /
Mic Input 1 & 2
+32 dB
Stereo Input 5
Stereo Input 6
AUG '12
DS861PP3
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Table of Contents
Related Manuals for Cirrus Logic CS5346
Summary of Contents for Cirrus Logic CS5346
- Page 1 +3.3 V Digital Power Supply, Nominal The CS5346 is available in a 48-pin LQFP package in Direct Interface with 3.3 V to 5 V Logic Levels Commercial (-40° to +85° C) grade. The CDB5346 Cus- ...
-
Page 2: Table Of Contents
CS5346 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - CS5346 ......................5 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..............7 3. CHARACTERISTICS AND SPECIFICATIONS ..................8 RECOMMENDED OPERATING CONDITIONS ................... 8 ABSOLUTE MAXIMUM RATINGS ....................... 8 ANALOG CHARACTERISTICS ......................9 ANALOG CHARACTERISTICS CONT....................10 DIGITAL FILTER CHARACTERISTICS .................... - Page 3 Figure 6.Control Port Timing - SPI Format ....................17 Figure 7.Typical Connection Diagram ....................... 18 Figure 8.Master Mode Clocking ........................ 20 Figure 9.Analog Input Architecture ......................21 Figure 10.CS5346 PGA ..........................22 Figure 11.1 V Input Circuit ........................22 Figure 12.1 V Input Circuit with RF Filtering ..................
- Page 4 CS5346 LIST OF TABLES Table 1. Speed Modes ..........................19 Table 2. Common Clock Frequencies ....................... 19 Table 3. Slave Mode Serial Bit Clock Ratios ..................... 20 Table 4. Device Revision .......................... 28 Table 5. Freeze-able Bits .......................... 28 Table 6. Functional Mode Selection ......................29 Table 7.
-
Page 5: Pin Descriptions - Cs5346
CS5346 1. PIN DESCRIPTIONS - CS5346 48 47 46 45 44 43 42 41 40 39 38 37 SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN AGND CS5346 AIN3A AIN3B PGAOUTB AIN2A PGAOUTA AIN2B AIN6B AIN1A AIN6A AIN1B MICBIAS 13 14 15 16 17 18 19 20 21 22 23 24... - Page 6 CS5346 AIN1A Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specifica- AIN1B tion table. AGND Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section.
-
Page 7: Pin Compatibility - Cs5345/Cs5346 Differences
CS5346 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES The CS5346 is p in compatible with the CS5345 and is a drop in replacement for CS5345 applications where VA = 5 V, VD = 3.3 V, VLS 3.3 V, and VLC 3.3 V. -
Page 8: Characteristics And Specifications
CS5346 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DGND = 0 V; All voltages with respect to ground. Parameters Symbol Units DC Power Supplies: Analog 4.75 5.25 Digital 3.13 3.47 Logic - Serial Port 3.13 5.25 Logic - Control Port 3.13... -
Page 9: Analog Characteristics
CS5346 ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V; = +25° C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz;... -
Page 10: Analog Characteristics Cont
CS5346 ANALOG CHARACTERISTICS CONT. Parameter Symbol Unit Line-Level Input and Programmable Gain Amplifier Gain Range - 12 + 12 Gain Step Size Absolute Gain Step Error Maximum Input Level 0.85*VA Input Impedance Selected inputs 28.8 43.2 k Un-selected inputs k... -
Page 11: Digital Filter Characteristics
CS5346 DIGITAL FILTER CHARACTERISTICS Parameter (Note 7) Symbol Unit Single-Speed Mode Passband (-0.1 dB) 0.4896 Passband Ripple 0.035 Stopband 0.5688 Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) 12/Fs Double-Speed Mode Passband (-0.1 dB) 0.4896 Passband Ripple 0.025 Stopband 0.5604... -
Page 12: Dc Electrical Characteristics
CS5346 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter Symbol Unit Power Supply Current VA = 5 V (Normal Operation) VD, VLS, VLC = 3.3 V... -
Page 13: Digital Interface Characteristics
CS5346 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 3.3 V. Parameters (Note 11) Symbol Units High-Level Input Voltage Serial Port 0.7xVLS Control Port 0.7xVLC Low-Level Input Voltage Serial Port 0.3xVLS... -
Page 14: Switching Characteristics - Serial Audio Port
CS5346 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VLS, C = 20 pF. (Note 12) Parameter Symbol Unit Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode MCLK Specifications MCLK Frequency 2.048... -
Page 15: Figure 1.Master Mode Serial Audio Port Timing
CS5346 LRCK Input sclkh sclkl SCLK Input sclkw SDOUT Figure 1. Master Mode Serial Audio Port Timing LRCK Output SCLK Output SDOUT Figure 2. Slave Mode Serial Audio Port Timing Channel B - Right Channel A - Left LRCK SCLK... -
Page 16: Switching Characteristics - Control Port - I²C Format
CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, C = 30 pF. Parameter Symbol Unit SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions µs... -
Page 17: Switching Characteristics - Control Port - Spi Format
CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, C = 30 pF. Parameter Symbol Units CCLK Clock Frequency RST Rising Edge to CS Falling CS High Time Between Transmissions s... -
Page 18: Typical Connection Diagram
CS5346 4. TYPICAL CONNECTION DIAGRAM +3.3V 0.1 µF 10 µF 10 µF 0.1 µF 3.3 µF +3.3V PGAOUTA to +5V 0.1 µF 3.3 µF PGAOUTB MCLK SCLK Digital Audio AIN1A Analog Input Left Analog Input 1 Capture LRCK SDOUT AIN1B... -
Page 19: Applications
3. The desired register settings can be loaded while the PDN bit remains set. 4. Clear the PDN bit to initiate the power-up sequence. System Clocking The CS5346 will operate at sa mpling frequencies from 8 kHz to 200 kHz. This range is div ided into three speed modes as shown in Table... -
Page 20: Master Mode
High-Pass Filter and DC Offset Calibration When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a D C level, possibly yielding clicks when switching between devices in a mul- tichannel system. -
Page 21: Analog Input Multiplexer, Pga, And Mic Gain
Analog Input Configuration for 1 V Input Levels The CS5346 PGA, excluding the input multiplexer, is shown in Figure 10 with nominal component values. Interfacing to this circuit is a relatively simple matter and several options are available. The simplest option is shown in Figure 11. -
Page 22: Analog Input Configuration For 2 Vrms Input Levels
5.5.2 Analog Input Configuration for 2 V Input Levels The CS5346 can also be easily configured to support an external 2 V input signal, as shown in Figure 13. In this configuration, the 2 V input signal is attenuated to 1.5 V at the analog input with the external 12 k... -
Page 23: Pga Auxiliary Analog Output
The control port has two modes: SPI and I²C, with the CS5346 acting as a slave device. SPI Mode is se- lected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state. -
Page 24: I²C Mode
SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS5346 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). -
Page 25: Interrupts And Overflow
Interrupts and Overflow The CS5346 has a comprehensive interrupt capability. The INT output pin is int e nded to drive the interrupt input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active-low, open-drain driver (see “Active High/Low (Bit 0)”... -
Page 26: Reset
CS5346s in the system. If only one master clock source is needed, one solution is to place one CS5346 in Master Mode, and slave all of the other CS5346s to the one master. -
Page 27: Register Quick Reference
CS5346 6. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0 pg. 28 Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC Reserved pg. 28... -
Page 28: Register Description
CS5346 7. REGISTER DESCRIPTION Chip ID - Register 01h PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0 Function: This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits (3 through 0) indicate the device revision as shown in Table 4 below. -
Page 29: Adc Control - Address 04H
CS5346 ADC Control - Address 04h Reserved Reserved Mute HPFFreeze 7.3.1 Functional Mode (Bits 7:6) Function: Selects the required range of sample rates. Mode Single-Speed Mode: 8 to 50 kHz sample rates Double-Speed Mode: 50 to 100 kHz sample rates... -
Page 30: Mclk Frequency - Address 05H
CS5346 MCLK Frequency - Address 05h MCLK MCLK MCLK Reserved Reserved Reserved Reserved Reserved Freq2 Freq1 Freq0 7.4.1 Master Clock Dividers (Bits 6:4) Function: Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings. MCLK Divider... -
Page 31: Channel A Pga Control - Address 08H
CS5346 Channel A PGA Control - Address 08h Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0 7.7.1 Channel A PGA Gain (Bits 5:0) Function: Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. -
Page 32: Analog Input Selection (Bits 2:0)
CS5346 PGASoft PGAZeroCross Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default) Table 11. PGA Soft Cross or Zero Cross Mode Selection 7.8.2 Analog Input Selection (Bits 2:0) Function: These bits are used to select the input source for the PGA and ADC. Please see... -
Page 33: Clock Error (Bit 3)
CS5346 7.10.1 Clock Error (Bit 3) Function: Indicates the occurrence of a clock error condition. 7.10.2 Overflow (Bit 1) Function: Indicates the occurrence of an ADC overflow condition. 7.10.3 Underflow (Bit 0) Function: Indicates the occurrence of an ADC underflow condition. -
Page 34: Parameter Definitions
CS5346 8. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. -
Page 35: Filter Plots
CS5346 9. FILTER PLOTS -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 17. Single-Speed Stopband Rejection Figure 18. -
Page 36: Figure 23.Double-Speed Transition Band (Detail)
CS5346 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 23. -
Page 37: Package Dimensions
CS5346 10.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING INCHES MILLIMETERS 0.055 0.063 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 0.007 0.009 0.011 0.17 0.22 0.27 0.343 0.354 0.366 8.70 9.0 BSC 9.30 0.272 0.28 0.280 6.90 7.0 BSC 7.10 0.343... -
Page 38: Ordering Information
TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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