Cirrus Logic EP93 Series User Manual page 233

VideoAttribs
31 30 29 28
15 14 13 12
INT INTEN PIFEN CCIREN
Address: 0x8003_0024
Default: 0x0000_0000
Definition: Video Signal Attributes register.
Bit Descriptions:
RSVD:
SDSEL:
BKPXD:
DVERT:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
27 26 25 24
RSVD
11 10 9 8
RSVD LCDEN ACEN INVCLK
Reserved - Unknown during read
SDRAM Selector - Read/Write
Writing to these two bits defines which SDCSn[3:0] pin is
used to access the video frame buffer in SDRAM:
00 SDCSn[0]
01 SDCSn[1]
10 SDCSn[2]
11 SDCSn[3]
SDCSn[3] is selected by default on hardware reset.
Blank Pixel Data - Read/Write
Writing BKPXD = '1' forces the pixel data on the P[17:0]
pins to be 0x0 when the blanking signal on the BLANK pin
is '0'.
0 - Disable
1 - Enable
This allows the use of an inexpensive external DAC that
does not contain data blanking logic.
Double Vertical - Read/Write
Writing DVERT = '1' forces the values of the defined bit-
fields in the VLinesTotal, VSyncStrtStop, VActiveStrtStop,
VBlankStrtStop, and
(2X programmed value) when used.
0 - Disable
1 - Enable
Copyright 2007 Cirrus Logic
23 22 21 20
SDSEL BKPXD
7 6 5 4
BLKPOL HSPOL V/CPOL CSYNC
VClkStrtStop
EP93xx User's Guide
19 18 17 16
DVERT DHORZ EQUSER INTRLC
3 2 1 0
DATEN SYNCEN PCLKEN EN
registers to be doubled
7-51
7