Cirrus Logic EP93 Series User Manual page 632

IrDA
EP93xx User's Guide
17
FIMR
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
17-36
RFS:
TAB:
TFC:
TFS:
29 28 27 26
13 12 11 10
RSVD
0x808B_0184 - Read/Write
0x0000_0000
FIR Interrupt Mask Register.
RSVD:
RFL:
RIL:
Copyright 2007 Cirrus Logic
Receive buffer Service Request (read only).
0 - Receive buffer is empty or the receiver is discarding
data or the receiver is disabled.
1 - Receive buffer is not empty and the receiver is
enabled, DMA service request signaled.
The bit is automatically cleared when the receive buffer is
emptied.
Transmit Frame Aborted. Set to "1" when a transmitted
frame is terminated with an abort. This will only occur if the
TUS bit is set in the IrCtrl register. The bit is cleared by
writing a "1" to this bit.
Transmitted Frame Complete. Set to "1" whenever a
transmitted frame completes (whether it is terminated with
a CRC followed by a stop flag or terminated with an abort).
This bit is cleared by writing a "1" to this bit.
Transmit buffer Service Request (read only).
0 - Transmit buffer is full or transmitter disabled.
1 - Transmit buffer is not full and the transmitter is
enabled, DMA service is signaled.
The bit is automatically cleared after the buffer is filled.
25 24 23 22
RSVD
9 8 7 6
RFL
Reserved. Unknown During Read.
RFL mask bit. When high, the FIR RFL status can
generate an interrupt.
RIL mask bit. When high, the FIR RIL status can generate
an interrupt.
21 20 19 18
5 4 3 2
RIL RFC RFS TAB
17 16
1 0
TFC TFS
DS785UM1