Cirrus Logic EP93 Series User Manual page 174

Vectored Interrupt Controller
EP93xx User's Guide
Definition:
6
Bit Descriptions:
VICxIntEnClear
31 30
15 14
Address:
Default: Don't Care
Definition:
Bit Descriptions:
VICxSoftInt
31 30
15 14
Address:
6-12
Interrupt Enable Register. The VICxIntEnable register enables the interrupt
requests by unmasking the interrupt sources. On reset, all interrupts are
disabled (masked).
IntEnable:
29 28 27 26
13 12 11 10
VIC1IntEnClear: 0x800B_0014 - Write Only
VIC2IntEnClear: 0x800C_0014 - Write Only
Interrupt Enable Clear Register. The VICxIntEnClear register clears bits in the
VICxIntEnable register.
IntEnable Clear:
29 28 27 26
13 12 11 10
VIC1SoftInt: 0x800B_0018 - Read/Write
VIC2SoftInt: 0x800C_0018 - Read/Write
Copyright 2007 Cirrus Logic
Enables the interrupt request lines:
1 - Interrupt enabled. Allows interrupt request to ARM
Core.
0 - Interrupt disabled.
25 24 23 22
IntEnable Clear
9 8 7 6
IntEnable Clear
Clears bits in the VICxIntEnable register. Writing a bit to
"1" clears the corresponding bit in the VICxIntEnable
register. Any bits written to "0" have no effect.
25 24 23 22
SoftInt
9 8 7 6
SoftInt
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1