Cirrus Logic EP93 Series User Manual page 801

PADR: 0x8084_0000 - Read/Write
PBDR: 0x8084_0004 - Read/Write
PCDR: 0x8084_0008 - Read/Write
PDDR: 0x8084_000C - Read/Write
PEDR: 0x8084_0020 - Read/Write
PFDR: 0x8084_0030 - Read/Write
PGDR: 0x8084_0038 - Read/Write
PHDR: 0x8084_0040 - Read/Write
Definition:
Port x Data Register. Values written to this 8-bit read/write register will be
output on port x pins if the corresponding data direction bits are set HIGH (port
output). Values read from this register reflect the external state of Port x
inputs. All bits are cleared by a system reset. ("X." stands for a letter, A
through H.)
Bit Descriptions:
RSVD:
PxDATA:
PxDDR
31 30 29 28
15 14 13 12
RSVD
Address:
PADDR: 0x8084_0010 - Read/Write
PBDDR: 0x8084_0014 - Read/Write
PCDDR: 0x8084_0018 - Read/Write
PDDDR: 0x8084_001C - Read/Write
PEDDR: 0x8084_0024 - Read/Write
PFDDR: 0x8084_0034 - Read/Write
PGDDR: 0x8084_003C - Read/Write
PHDDR: 0x8084_0044 - Read/Write
Definition:
Port x Data Direction Register. Bits cleared in this 8-bit read/write register will
select the corresponding pin in port x to become an input, setting a bit sets the
pin to output. All bits are cleared by a system reset. ("X." stands for a letter, A
through H.)
Bit Descriptions:
RSVD:
DS785UM1
Reserved. Unknown During Read.
Port x 8-bit data.
27 26 25 24
RSVD
11 10 9 8
Reserved. Unknown During Read.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
PxDIR
GPIO Interface
EP93xx User's Guide
19 18 17 16
3 2 1 0
28-11
28