Cirrus Logic EP93 Series User Manual page 570

UART2
EP93xx User's Guide
UART2Ctrl
31 30
15 14
15
Address:
Default:
Definition:
Bit Descriptions:
15-12
29 28 27 26
13 12 11 10
RSVD
0x808D_0014 - Read/Write
0x0000_0000
UART Control Register
RSVD:
LBE:
RTIE:
TIE:
RIE:
MSIE:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
LBE RTIE
Reserved. Unknown During Read.
Loopback Enable, for SIR and UART only.
1 - If the SIR Enable bit is also set to "1", and register
UART2TMR bit 1 (SIRTEST) is set to "1", the SIR output
path is inverted and fed through to the SIR input path. The
SIRTEST bit in the test register must be set to "1" to
override the normal half-duplex SIR operation. This should
be the requirement for accessing the test registers during
normal operation, and SIRTEST must be cleared to "0"
when loopback testing is finished. This feature reduces the
amount of external coupling required during system test.
0 - This bit is cleared to "0" on reset, which disables the
loopback mode.
Receive Timeout Enable. If this bit is set to "1", the receive
timeout interrupt is enabled.
Transmit Interrupt Enable. If this bit is set to "1", the
transmit interrupt is enabled.
Receive Interrupt Enable. If this bit is set to "1", the receive
interrupt is enabled.
Modem Status Interrupt Enable. If this bit is set to "1", the
modem status interrupt is enabled.
21 20 19 18
5 4 3 2
TIE RIE MSIE SIRLP
17 16
1 0
SIREN UARTE
DS785UM1