Registers; Table 19-1. Watchdog Timer Register Memory Map - Cirrus Logic EP93 Series User Manual

Note: A software reset can reset the system without this register losing its contents.

19.1 Registers

Address
0x8094_0000
0x8094_0004
Note: Watchdog registers are intended to be word-accessed only. Since the least significant
bytes of the address bus are not decoded, byte and half word accesses are not allowed
and may have unpredictable results.
Register Descriptions
Watchdog
31 30 29 28 27
15 14 13 12 11
CTL
Address:
0x8094_0000 - Read/Write
Default:
0x0000_0000
Definition:
Watchdog control register.
Bit Descriptions:
RSVD:
WRITE ONLY BIT FIELDS
CTL:
DS785UM1

Table 19-1. Watchdog Timer Register Memory Map

Name SW locked
"Watchdog" No Read/Write
"WDStatus" No Read/Write
26 25 24 23
10 9 8 7
CTL/PLSDSN
Reserved. Unknown during read.
Watchdog control bits. The ARM Core writes 0x5555 to
this half-word to periodically restart the watchdog timer.
Writing 0xAA55 to this hword will disable the watchdog
timer. Writing 0xAAAA to this hword will re-enable the
watchdog timer.
Copyright 2007 Cirrus Logic
Type Size
16/3 bits Watchdog Control Register
7 bits Watchdog Status Storage Register
22 21 20
RSVD
6 5 4
CTL/OVRID CTL/SWDIS
Watchdog Timer
EP93xx User's Guide
Description
19 18 17
3 2 1
CTL/HWDIS CTL/URST CTL/3KRST
19
16
0
CTL/WD
19-3