Cirrus Logic EP93 Series User Manual page 683

i2s_mstr:
i2s_trel:
i2s_tckp:
i2s_tlrs:
I2SRXClkCfg
31 30 29 28
15 14 13 12
Address:
0x8082_0004 - Read/Write
Default:
0x0000_0000
Definition:
Receiver clock configuration register.
Bit Descriptions:
RSVD:
DS785UM1
Defines if the TX Audio clocks are
slave or master.
0 - slave mode.
1 - master mode.
Determines the timing of the lrckt with respect to the sdox
data outputs.
0 - Transition of lrckt occurs together with the first data bit.
1 - Transition of lrckt occurs one bitclk cycle before the first
sdox data bit. This is I
Defines polarity of the TX bitclk.
1 - Positive clock polarity. The lrckt and sdox lines change
synchronously with the positive edge of the bitclk and are
considered valid during negative transitions.
0 - Negative clock polarity. The lrckt and sdox lines change
synchronously with the negative edge of the bitclk and are
considered valid during positive transitions.
Defines the polarity of lrckt.
0 - if lrckt is low, then it is the left word, if lrckt is high, then
it is the right word.
1 - if lrckt is low, then it is the right word, if lrckt is high,
then it is the left word.
27 26 25 24
11 10 9 8
RSVD
Reserved. Unknown During Read.
Copyright 2007 Cirrus Logic
2
S format.
23 22 21 20
RSVD
7 6 5 4
i2s_rx_bcr i2s_rx_nbcg
2
I S Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
i2s_mstr i2s_rrel i2s_rckp i2s_rlrs
21-27
21