Table 7-15. Output Shift Mode Table; Table 7-16. Bits Per Pixel Scanned Out - Cirrus Logic EP93 Series User Manual

S:
P:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
Table 7-14. Blink Mode Definition Table (Continued)
M3 M2 M1 M0
0 1 0 1
0 1 1 0
0 1 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Shift - Read/Write
The Shift Mode is specified by selecting a value from
Table 7-15

Table 7-15. Output Shift Mode Table

S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0 Dual Scan 2 2/3 3-bit pixels per clock over 8-bit bus
1 1 1
Pixel - Read/Write
The number of bits per pixel that are output on the P[x]
pins is specified by selecting a value from
writing it to this field.
The Graphics Engine has a separate setting for this value,
which may or may not be the same.

Table 7-16. Bits per Pixel Scanned Out

P2 P1 P0
0 0 0
0 0 1
0 1 0
0 1 1
Copyright 2007 Cirrus Logic
Blink Mode
Blink to offset color single value mode
Blink to offset color 888 mode (555,565)
Undefined
Blink dimmer single value mode
Blink brighter single value mode
Blink dimmer 888 mode (555,565)
Blink brighter 888 mode (555,565)
and writing it to this field.
Shift Mode
1 - pixel per pixel clock (up to 24 bits wide)
1 - pixel mapped to 18 bits each pixel clock
2 - pixels per shift clock (up to 9 bits wide each)
4 - pixels per shift clock (up to 4 bits wide each)
8 - pixels per shift clock (up to 2 bits wide each)
2 2/3 3-bit pixels per clock over 8 bit bus
Undefined - Defaults to 1 - pixel per pixel clock
Pixel Mode
pixel multiplexer disabled
4 bits per pixel
8 bits per pixel
do not use
EP93xx User's Guide
Table 7-16 and
7-59
7