Cirrus Logic EP93 Series User Manual page 540

UART1 With HDLC and Modem Control Signals
EP93xx User's Guide
UART1RXSts
31 30
15 14
14
Address:
Default:
Definition:
Bit Descriptions:
14-18
29 28 27 26
13 12 11 10
RSVD
0x808C_0004 - Read/Write
0x0000_0000
UART1 Receive Status Register/Error Clear Register. Provides receive status
of the data value last read from the UART1Data. A write to this register clears
the framing, parity, break and overrun errors. The data value is not important.
Note that BE, PE and FE are not used for synchronous HDLC.
RSVD:
OE:
BE:
PE:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
Reserved. Unknown During Read.
Overrun Error. This bit is set to "1" if data is received and
the FIFO is already full. This bit is cleared to "0" by a write
to UART1RXSts. The FIFO contents remain valid since no
further data is written when the FIFO is full. Only the
contents of the shift register are overwritten. The data
must be read in order to empty the FIFO.
Break Error. This bit is set to 1 if a break condition was
detected, indicating that the received data input was held
LOW for longer than a full-word transmission time (defined
as start, data, parity and stop bits). This bit is cleared to 0
after a write to UART1RXSts. In FIFO mode, this error is
associated with the character at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive
data input goes to a 1 (marking state) and the next valid
start bit is received.
Parity Error. When this bit is set to 1, it indicates that the
parity of the received data character does not match the
parity selected in UART1LinCtrlHigh (bit 2). This bit is
cleared to 0 by a write to UART1RXSts. In FIFO mode,
this error is associated with the character at the top of the
FIFO.
21 20 19 18
5 4 3 2
OE BE
17 16
1 0
PE FE
DS785UM1