Table 28-3. Ep9312 Gpio Port To Pin Map - Cirrus Logic EP93 Series User Manual

4. EEDAT is the EEPROM data pin.
5. ROW[7:0] are the Key Matrix row pins.
6. COL[7:0] are the Key Matrix column pins.
Pin
Name Function
EGPIO[7:0]
EGPIO[15:8]
3
GRLED
4
RDLED
5
EECLK
6
EEDAT
SLA[1:0] Port G3:2
7
ROW[7:0]
ROW[7:0]
8
COL[7:0]
1
IDEDA[2:0]
IDEDA[2:0]
1
IDECS1n
1
IDECS0n
1
DIORn
2
DD[15:12]
DD[15:12]
2
DD[11:8]
2
DD[7:0]
1. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.
2. DD[15:0] are the IDE data pins. DD[11:8] has no GPIO pin mapping.
3. GRLED is the Green LED pin.
4. RDLED is the Red LED pin.
5. EECLK is the EEPROM clock pin.
6. EEDAT is the EEPROM data pin.
7. ROW[7:0] are the Key Matrix row pins.
8. COL[7:0] are the Key Matrix column pins.
DS785UM1

Table 28-3. EP9312 GPIO Port to Pin Map

Function in
Default
GonK
Mode
Port A Port A
Port B Port B
Port E0 Port E0
Port E1 Port E1
Port G0 Port G0
Port G1 Port G1
Port G3:2
Port C
COL[7:0] Port D
IDEDA[2:0]
IDECS1n IDECS1n
IDECS0n IDECS0n
DIORn DIORn
DD[15:12]
DD[11:8] DD[11:8]
DD[7:0] DD[7:0]
Copyright 2007 Cirrus Logic
Function in Function in
EonIDE GonIDE
Mode Mode
Port A Port A
Port B Port B
Port E0 Port E0
Port E1 Port E1
Port G0 Port G0
Port G1 Port G1
Port G3:2 Port G3:2
ROW[7:0] ROW[7:0]
COL[7:0] COL[7:0]
Port E7:5 IDEDA[2:0]
Port E4 IDECS1n
Port E3 IDECS0n
Port E2 DIORn
DD[15:12] Port G7:4
DD[11:8] DD[11:8]
DD[7:0] DD[7:0]
GPIO Interface
EP93xx User's Guide
Function in
HonIDE
Mode
Port A
Port B
Port E0
Port E1
Port G0
Port G1
Port G3:2
ROW[7:0]
COL[7:0]
IDEDA[2:0]
IDECS1n
IDECS0n
DIORn
DD[15:12]
DD[11:8]
Port H
28-7
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