Apb Slave; Register Definitions; Table 2-4. Arm920T Core Operating Modes - Cirrus Logic EP93 Series User Manual

Note: Due to decoding optimization, the APB peripheral registers are aliased throughout each
peripherals register bank. Do not attemp to access an unspecified register within the bank.

2.3.3 APB Slave

An APB Slave responds to accesses initiated by bus masters. The slave uses signals from
the decoder to determine when it should respond to a bus access. All other signals required
for the access, such as the address and control information, are generated by the AHB-to-
APB Bridge.

2.3.4 Register Definitions

The ARM920T Core has thirty seven 32-bit internal registers, where some are modal and
some are banked. If operating in Thumb instructions state, the ARM Core must switch to
ARM instructions state before taking an exception. The return instruction will restore the ARM
Core to the Thumb state. Most tasks are executed out of User mode. The ARM920T Core's
operating modes are shown in
Table 2-5 illustrates the use of all registers for the ARM920T Core's operating modes. Each
will bank or store a specific number of registers. Banked register information is not shared
between modes. FIQs bank the largest number of registers, and increase performance by
reducing the need to push/pop registers from the stack.
DS785UM1
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-4.

Table 2-4. ARM920T Core Operating Modes

Mode
User Unprivileged normal operating mode
Fast interrupt (high priority) mode when FIQ is
FIQ
asserted
Interrupt request (normal) mode when IRQ is
IRQ
asserted
Software interrupt instruction (SWI) or reset will
Supervisor
cause entry into this mode.
Memory access violation will cause entry into this
Abort:
mode.
Undef Undefined instructions mode
Privileged mode. Uses same registers as User
System
mode
Copyright 2007 Cirrus Logic
EP93xx User's Guide
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