Cirrus Logic EP93 Series User Manual page 262

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
Bit Descriptions:
7
HSigStrtStop
31 30
RSVD
15 14
RSVD
Address: 0x8003_020C
Default: 0x0000_0000
Definition: Horizontal Signature Bounds Start/Stop register
Bit Descriptions:
7-80
RSVD:
STOP:
STRT:
29 28 27 26
13 12 11 10
RSVD:
STOP:
STRT:
Copyright 2007 Cirrus Logic
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VSIGEN signal becomes inactive (stops).This
indicates the end of the signature calculation for the
Vertical frame. VSIGEN is an internal block signal. The
SIG_ENABLE control to the video signature analyzer is
enabled by the logical AND of VSIGEN and HSIGEN.
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VSIGEN signal becomes active (starts).This
indicates the start of the signature calculation for the
Vertical frame. VSIGEN is an internal block signal. The
SIG_ENABLE control to the video signature analyzer is
enabled by the logical AND of VSIGEN and HSIGEN.
25 24 23 22
9 8 7 6
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the horizontal down
counter at which the HSIGEN signal becomes inactive
(stops). This indicates the end of the signature calculation
for a horizontal line. HSIGEN is an internal block signal.
The SIG_ENABLE control to the video signature analyzer
is enabled by the logical AND of VSIGEN and HSIGEN.
Start - Read/Write
21 20 19 18
STOP
5 4 3 2
STRT
17 16
1 0
DS785UM1