Cirrus Logic EP93 Series User Manual page 800

Arm 9 embedded processor family
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GPIO Interface
EP93xx User's Guide
28
1. A read from the data register returns the value of the GPIO module input port. These ports have a
default pin assignment. The read value default is the pin state based on the default pin map.
2. Port E bits 1 and 0 provide the LED driver function. The Port E[1:0] defaults to drive high. A read from
the Port E data register would be expected to return 0x03, if the other pins mapped to Port E inputs are
zero. However since the Port E[7:2] inputs are mapped to IDE control signals, the default read value will
depend on the default action of the IDE controller and the external interface.
3. The RAWSTATUSx registers have pin dependent default read states. The interrupt control registers
default to low level sensitive interrupt on reset. Therefore the external pin state will ripple through the
interrupt logic to determine the RAWSTATUSx default.
Register Descriptions
PxDR
31
30
15
14
Address:
28-10
Table 28-5. GPIO Register Address Map (Continued)
Address
Read Location
0x8084_0050
GPIOFIntType2
0x8084_0054
Reserved, Read undefined
0x8084_0058
GPIOFIntEn
0x8084_005C
IntStsF
0x8084_0060
RawIntStsF
0x8084_0064
GPIOFDB
0x8084_0090
GPIOAIntType1
0x8084_0094
GPIOAIntType2
0x8084_0098
0x8084_009C
GPIOAIntEn
0x8084_00A0
IntStsA
0x8084_00A4
RawIntStsA
0x8084_00A8
GPIOADB
0x8084_00AC
GPIOBIntType1
0x8084_00B0
GPIOBIntType2
0x8084_00B4
0x8084_00B8
GPIOBIntEn
0x8084_00BC
IntStsB
0x8084_00C0
RawIntStsB
0x8084_00C4
GPIOBDB
0x8084_00C8
EEDrive
29
28
27
26
13
12
11
10
RSVD
Type
R/W
Write Only
R/W
Read only
Read only
R/W
R/W
R/W
-
Write Only
R/W
Read only
Read only
R/W
R/W
R/W
-
Write Only
R/W
Read only
Read only
R/W
R/W
25
24
23
22
RSVD
9
8
7
6
Copyright 2007 Cirrus Logic
Write Location
GPIOFIntType2
GPIOFEOI
GPIOFIntEn
-
-
GPIOFDB
GPIOAIntType1
GPIOAIntType2
GPIOAEOI
GPIOAIntEn
-
-
GPIOADB
GPIOBIntType1
GPIOBIntType2
GPIOBEOI
GPIOBIntEn
-
-
GPIOBDB
EEDrive
21
20
19
18
5
4
3
2
PxDATA
Reset Value
0x00
0x00
0x00
0x00
Note 3
0x00
0x00
0x00
-
0x00
0x00
Note 3
0x00
0x00
0x00
-
0x00
0x00
Note 3
0x00
0x00
17
16
1
0
DS785UM1

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