Figure 5-2. Clock Generation System - Cirrus Logic EP93 Series User Manual

System Controller
EP93xx User's Guide
5
5.1.5.2.1 Bus Clock Generation
Figure 5-3
and the APB bus clock (PCLK).
5-6
32 KHz Oscillator
14.7456 MHz Oscillator
PLL1
PLL1 CFG
PLL2
PLL2 CFG

Figure 5-2. Clock Generation System

shows the generated clocks: the CPU clock (FCLK), the AHB bus clock (HCLK),
Copyright 2007 Cirrus Logic
Syscon
32 KHz
Divide
Peripheral
Clocks
CPU and
Bus Clocks
USB and
FIR Clocks
Video
Clocks
CPU and
Audio
Bus Clocks
Clocks
MIR
Clock
Key
Touch
Clock
WATCH_CLK
UARTxCLK
SSPCLK
PWMCLK
Timer Clocks
FCLK
HCLK
PCLK
USBHost48MHz
USBHost12MHz
FIR_CLK
VCLK
SCLK
LRCLK
MCLK
MIR_CLK
KEY_CLK
TOUCH_CLK
ADC_CLK
FILT_CLK
DS785UM1