Cirrus Logic EP93 Series User Manual page 583

UART3LinCtrlMid
31 30 29 28
15 14 13 12
Address:
0x808E_000C - Read/Write
Default:
0x0000_0000
Definition:
UART3 Line Control Register Middle
Bit Descriptions:
RSVD:
BR:
UART3LinCtrlLow
31 30 29 28
15 14 13 12
Address:
0x808E_0010 - Read/Write
Default:
0x0000_0000
Definition:
UART3 Line Control Register Low.
Bit Descriptions:
RSVD:
DS785UM1
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
Baud Rate Divisor bits [15:8]. Most significant byte of baud
rate divisor. These bits are cleared to 0 on reset.
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
Copyright 2007 Cirrus Logic
24 23 22 21
RSVD
8 7 6 5
24 23 22 21
RSVD
8 7 6 5
UART3 With HDLC Encoder
EP93xx User's Guide
20 19 18 17
4 3 2 1
BR
20 19 18 17
4 3 2 1
BR
16
0
16
16
0
16-7