Cirrus Logic EP93 Series User Manual page 492

Static Memory Controller
EP93xx User's Guide
12
PCCommon
31 30
WC
15 14
RSVD
Address: 0x8008_0024 - Read/Write
Default: 0x0000_0000
Definition: PC Card Common register
Bit Descriptions:
12-14
HA:
PA:
29 28 27 26
RSVD
13 12 11 10
HC
RSVD:
WC:
AC:
Copyright 2007 Cirrus Logic
The data strobe assertion time is specified by (AA+1)
HCLK cycles. For example, if AA = 0x10, the data strobe
assertion time is 16 + 1 = 17 cycles of HCLK
Attribute space Hold time - Read/Write
The value written to this field specifies the minimum
'number of HCLK cycles, minus 1' between de-asserting
the data strobe, MCDAENn
strobe, MCADENn.
The Hold time is specified by (HA +1) HCLK cycles. For
example, if HA = 0xC, the Hold time is 12 + 1 = 13 cycles
of HCLK.
Attribute space setup time - Read/Write
The value written to this field specifies the 'number of
HCLK cycles, minus 1' that the address strobe,
MCADENn, is set up before assertion of the data strobe,
MCDAENn.
The Setup time is specified by (PA+1) HCLK cycles. For
example, if PA = 0x25, the Setup time is 37 + 1 = 38 cycles
of HCLK.
25 24 23 22
9 8 7 6
Reserved - Unknown During Read
Common Space Width - Read/Write
The value written to this bit specifies the bus-width of the
Common space:
0 - 8-bit wide Common space
1 - 16-bit wide Common space
Common Space Access time - Read/Write
and de-asserting the address
,
21 20 19 18
AC
5 4 3 2
PC
17 16
1 0
DS785UM1