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Cirrus Logic CS42426 Manual

114 db, 192 khz 6-ch codec with pll
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114 dB, 192 kHz 6-Ch Codec with PLL
Features
Six 24-bit D/A, two 24-bit A/D converters
114 dB DAC / 114 dB ADC dynamic range
-100 dB THD+N
System sampling rates up to 192 kHz
Integrated low-jitter PLL for increased system
jitter tolerance
PLL clock or OMCK system clock selection
7 configurable general purpose outputs
ADC high pass filter for DC offset calibration
Expandable ADC channels and one-line
mode support
Digital output volume control with soft ramp
Digital +/-15 dB input gain adjust for ADC
Differential analog architecture
Supports logic levels between 5 V and 1.8 V
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
MUTEC
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
Advance Product Information
Cirrus Logic, Inc.
www.cirrus.com
VA AGND
REFGND VQ
GPO
Mute
ADC#1
Digital Filter
ADC#2
Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
General Description
The CS42426 CODEC provides two analog-to-digital and six
digital-to-analog Delta-Sigma converters, as well as an inte-
grated PLL, in a 64-pin LQFP package.
The CS42426 integrated PLL provides a low-jitter system
clock. The internal stereo ADC is capable of independent chan-
nel gain control for single-ended or differential analog inputs.
All six channels of DAC provide digital volume control and dif-
ferential analog outputs. The general purpose outputs may be
driven high or low, or mapped to a variety of DAC mute controls
or ADC overflow indicators.
The CS42426 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.
ORDERING INFORMATION
CS42426-CQZ
CS42426-DQZ
CDB42428
FILT+
OMCK
RMCK
Mult/Div
Internal Voltage
Reference
PLL
ADC
Gain & Clip
Serial
Audio
Gain & Clip
Port
Cirrus Logic, Inc. 2004
(All Rights Reserved)
CS42426
-10° to 70° C
64-pin LQFP
-40° to 85° C
64-pin LQFP
Evaluation Board
DGND VD
LPFLT
VLC
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/CDOUT
SCL/CCLK
ADCIN1
ADCIN2
ADC_SDOUT
ADC_LRCK
ADC_SCLK
VLS
DAC_LRCK
DAC_SCLK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
JUL '04
DS604A2
1

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Summary of Contents for Cirrus Logic CS42426

  • Page 1 AOUTA3- AOUTB3+ DAC#6 AOUTB3- This document contains information for a new product. Advance Product Information Cirrus Logic reserves the right to modify this product without notice. Cirrus Logic, Inc. www.cirrus.com Copyright Cirrus Logic, Inc. 2004 JUL ‘04 (All Rights Reserved)

  • Page 2: Table Of Contents

    I C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
  • Page 3 CS42426 3.6.1 SPI Mode ......................26 3.6.2 I2C Mode ......................27 3.7 Interrupts ......................... 28 3.8 Reset and Power-up ....................... 29 3.9 Power Supply, Grounding, and PCB layout ..............29 4 REGISTER QUICK REFERENCE ................... 30 5 REGISTER DESCRIPTION ..................... 32 5.1 Memory Address Pointer (MAP) ..................
  • Page 4 CS42426 LIST OF FIGURES Figure 1. Typical Connection Diagram .................... 8 Figure 2. Typical Connection Diagram using the PLL ..............9 Figure 3. Full-Scale Analog Input ....................10 Figure 4. Full-Scale Output ......................12 Figure 5. ATAPI Block Diagram (x = channel pair 1, 2, 3)............. 13 Figure 6.
  • Page 5 CS42426 Figure 52. Quad Speed (slow) Stopband Rejection..............60 Figure 53. Quad Speed (slow) Transition Band ................60 Figure 54. Quad Speed (slow) Transition Band (detail) ..............60 Figure 55. Quad Speed (slow) Passband Ripple ................60 Figure 56. Serial Audio Port Master Mode Timing ................ 61 Figure 57.

  • Page 6: Pin Descriptions

    CS42426 1 PIN DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DAC_SDIN1 G PO 1 DAC_SCLK G PO 2 DAC_LRCK G PO 3 G PO 4 DG ND G PO 5...
  • Page 7 ADCs. ADCIN1 External ADC Serial Input ( Input ) - The CS42426 provides for up to two external stereo analog to digital ADCIN2 converter inputs to provide a maximum of six channels on one serial data output line when the CS42426 is placed in One Line mode.

  • Page 8: Typical Connection Diagrams

    CS42426 2 TYPICAL CONNECTION DIAGRAMS +3.3 V to +5 V +5 V 0.01 µF 0.1 µF + 0.1 µF 0.01 µF 10 µF 10 µF 0.01 µF 0.1 µF + 0.1 µF 0.01 µF 10 µF 10 µF AOUTA1+ Analog Conditioning...

  • Page 9: Figure 2. Typical Connection Diagram Using The Pll

    CS42426 +3.3 V to +5 V +5 V 0.01 µF 0.1 µF + 0.1 µF 0.01 µF 10 µF 10 µF 0.01 µF 0.1 µF + 0.1 µF 0.01 µF 10 µF 10 µF AOUTA1+ Analog Conditioning and Muting AOUTA1-...

  • Page 10: Applications

    Figure 1 shows the recommended connections for the CS42426. The CS42426 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM bits in register “Functional Mode (address 03h)” on page 33. Single-Speed mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio.

  • Page 11: External Input Filter

    This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS42426 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time.

  • Page 12: Interpolation Filter

    CS42426 The CS42426 is a linear phase design and does not include phase or amplitude compensation for an exter- nal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external an- alog circuitry. Figure 4 shows the full-scale analog output levels.

  • Page 13: Atapi Specification

    “General Purpose Pin Control (addresses 29h to 2Fh)” on page 48. 3.3.4 ATAPI Specification The CS42426 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 15 on page 44 and Figure 5 for additional infor- mation.

  • Page 14: Clock Generation

    Clock Generation The clock generation for the CS42426 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input.

  • Page 15: Omck System Clock Mode

    CS42426 sample rate applications are shown in Table 1. The lock time is the worst case for an Fs transition from un- locked state to locking to 192 kHz. Fs Range (kHz) RFILT (kΩ) CFILT (pF) CRIP (pF) Settling time...

  • Page 16: Digital Interfaces

    The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS42426 (master mode), or it may be generated by an external source (slave mode). As described in later sections, particular modes of operation do allow the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.

  • Page 17: Table 5. Serial Audio Port Channel Allocations

    CS42426 bits in the register “Interface Formats (address 04h)” on page 34. The serial audio data is presented in 2's complement binary form with the MSB first in all formats. DAC_SDIN1, DAC_SDIN2, and DAC_SDIN3 are the serial data input pins supplying the internal DAC.

  • Page 18: Serial Audio Interface Formats

    CS42426 3.5.2 Serial Audio Interface Formats The DAC_SP and ADC_SP digital audio serial ports support 5 formats with varying bit depths from 16 to 24 as shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11. These formats are selected using the configuration bits in the registers, “Functional Mode (address 03h)”...

  • Page 19: Figure 8. I 2 S Serial Audio Formats

    CS42426 DA C_LR CK Le ft C h a nn e l R ig h t C ha n n e l AD C_LR CK DAC _SC LK ADC _SC LK D AC_ SDIN x +5 +4 +3 +2 +1...

  • Page 20: Figure 10. One Line Mode #1 Serial Audio Format

    CS42426 64 clks 64 clks D AC _LRCK Left Channel Right C hannel ADC _LRCK D AC_SCLK AD C_SCLK M SB M SB LS B M SB LS B M SB M SB LS B M SB M SB DAC _SDIN1...

  • Page 21: Adcin1/Adcin2 Serial Data Format

    Figure 12. ADCIN1/ADCIN2 Serial Audio Format For proper operation, the CS42426 must be configured to select which SCLK/LRCK is being used to clock the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 36, must be set accordingly.

  • Page 22: One Line Mode(Olm) Configurations

    CS42426 3.5.4 One Line Mode(OLM) Configurations 3.5.4.1 OLM Config #1 One Line Mode Configuration #1 can support up to 6 channels of DAC data, and 6 channels of ADC data. This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.

  • Page 23: Figure 14. Olm Configuration #2

    CS42426 3.5.4.2 OLM Config #2 This configuration will support up to 6 channels of DAC data, 6 channels of ADC data and will handle up to 20-bit samples at a sampling frequency of 96 kHz on all channels for both the DAC and ADC. The out- put data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run at the DAC Serial Port sample frequency.

  • Page 24: Figure 15. Olm Configuration #3

    CS42426 3.5.4.3 OLM Config #3 This configuration will support up to 6 channels of DAC data, and 6 channels of ADC data. OLM Config #3 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz.

  • Page 25: Figure 16. Olm Configuration #4

    CS42426 3.5.4.4 OLM Config #4 This One-Line Mode configuration can support up to 6 channels of DAC data on 2 DAC_SDIN pins, and 2 channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.

  • Page 26: Control Port Description And Timing

    3.6.1 SPI Mode In SPI mode, CS is the CS42426 chip select signal, CCLK is the control port bit clock (input into the CS42426 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

  • Page 27: I2C Mode

    All other transitions of SDA occur while the clock is low. The first byte sent to the CS42426 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write).

  • Page 28: Interrupts

    Interrupts The CS42426 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter- rupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with no active pull-up transistor.

  • Page 29: Reset And Power-Up

    When RST is low, the CS42426 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes opera- tional and the desired settings should be loaded into the control registers.

  • Page 30: Register Quick Reference

    CS42426 4 REGISTER QUICK REFERENCE Addr Function Chip_ID3 Chip_ID2 Chip_ID1 CHIP_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 default Power Control Reserved PDN_PLL PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 default Functional Mode DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 Reserved ADC_CLK DAC_DEM Reserved default Interface Formats DIF1...
  • Page 31 CS42426 Addr Function Mixing Ctrl Pair 2 P2_A=B Reserved Reserved P2_ATAPI4 P2_ATAPI3 P2_ATAPI2 P2_ATAPI1 P2_ATAPI0 default Mixing Ctrl Pair 3 P3_A=B Reserved Reserved P3_ATAPI4 P3_ATAPI3 P3_ATAPI2 P3_ATAPI1 P3_ATAPI0 default Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default ADC Left Ch.

  • Page 32: Register Description

    Chip_ID1 CHIP_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 5.2.1 CHIP I.D. (CHIP_IDX) Default = 1110 Function: I.D. code for the CS42426. Permanently set to 1110. 5.2.2 CHIP REVISION (REV_IDX) Default = 0001 Function: CS42426 revision level. Revision C is coded as 0011.

  • Page 33: Power Control (Address 02H)

    CS42426 Power Control (address 02h) Reserved PDN_PLL PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 5.3.1 POWER DOWN PLL (PDN_PLL) Default = 0 Function: When enabled, the PLL will remain in a reset state. It is advised that any change of this bit be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audi- ble artifacts.

  • Page 34: Interface Formats (Address 04H)

    CS42426 5.4.2 ADC FUNCTIONAL MODE (ADC_FMX) Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 192 kHz sample rates) 11 - Reserved Function: Selects the required range of sample rates for the ADC serial port(ADC_SP).

  • Page 35: Table 7. Digital Interface Formats

    CS42426 DIF1 DIF0 Description Format Figure Left Justified, up to 24-bit data S, up to 24-bit data Right Justified, 16-bit or 24-bit data reserved Table 7. Digital Interface Formats 5.5.2 ADC ONE_LINE MODE (ADC_OLX) Default = 00 Function: These bits select which mode the ADC will use. By default one-line mode is disabled but can be se- lected using these bits.

  • Page 36: Misc Control (Address 05H)

    CS42426 Misc Control (address 05h) Ext ADC SCLK HiZ_RMCK Reserved FREEZE FILT_SEL HPF_FREEZE DAC_SP ADC_SP 5.6.1 EXTERNAL ADC SCLK SELECT (EXT ADC SCLK) Default = 0 Function: This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using one line mode of operation.

  • Page 37: Clock Control (Address 06H)

    CS42426 5.6.6 DAC SERIAL PORT MASTER/SLAVE SELECT (DAC_SP M/S) Default = 1 Function: In Master mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave mode, DAC_SCLK and DAC_LRCK become inputs.

  • Page 38: Table 11. Omck Frequency Settings

    Default = 0 0 - Disabled 1 - Enabled Function: When enabled, the internal PLL of the CS42426 will lock to the LRCK of the ADC serial port (ADC_LRCK) while the ADC_SP is in slave mode. 5.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)

  • Page 39: Omck/Pll_Clk Ratio (Address 07H) (Read Only)

    Default = xxxh Function: The CS42426 will auto-detect the ratio between the OMCK and the recovered clock from the PLL, which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can be determined, and this information is displayed according to the following table. If the absolute fre- quency of the PLL clock does not match one of the given frequencies, this register will display the closest available value.

  • Page 40: Volume Control (Address 0Dh)

    CS42426 5.10 Volume Control (address 0Dh) Reserved SNGVOL SZC1 SZC0 AMUTE MUTE ADC_SP RAMP_UP RAMP_DN 5.10.1 SINGLE VOLUME CONTROL (SNGVOL) Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register and the other Volume Control registers are ignored.

  • Page 41: Channel Mute (Address 0Eh)

    CS42426 The Digital-to-Analog converters of the CS42426 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the MUTEC pin will go active during the mute period.

  • Page 42: Volume Control (Addresses 0Fh, 10H, 11H, 12H, 13H, 14H)

    CS42426 5.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) xx_VOL7 xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0 5.12.1 VOLUME CONTROL (XX_VOL) Default = 0 Function: The Digital Volume Control registers allow independent control of the signal levels in 0.5 dB incre- ments from 0 to -127 dB.
  • Page 43 CS42426 5.14.1 CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B) Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control registers when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Volume Control registers (per A-B pair), and the B Channel Volume Control registers are ignored when this function is enabled.

  • Page 44: Table 15. Atapi Decode

    5.14.2 ATAPI CHANNEL MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42426 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 15 and Figure 5 for additional information. ATAPI4...

  • Page 45: Adc Left Channel Gain (Address 1Ch)

    CS42426 5.15 ADC Left Channel Gain (address 1Ch) Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0 5.15.1 ADC LEFT CHANNEL GAIN (LGAINX) Default = 00h Function: The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and Zero Cross bits (SZC[1:0]) from +15 to -15 dB.

  • Page 46: Interrupt Status (Address 20H) (Read Only)

    Default = 0 Function: PLL unlock status bit. This bit will go high if the PLL becomes unlocked. 5.18.2 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42426 ADC signal path.

  • Page 47: Interrupt Mask (Address 21H)

    CS42426 5.19 Interrupt Mask (address 21h) UNLOCKM Reserved Reserved Reserved Reserved Reserved OverFlowM Reserved Default = 00000000 Function: The bits of this register serve as a mask for the interrupt sources found in the register “Interrupt Status (address 20h) (Read Only)” on page 46. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register.

  • Page 48: General Purpose Pin Control (Addresses 29H To 2Fh)

    CS42426 5.21.2 CHANNEL MUTES SELECT (M_AOUTXX) Default = 1111 0 - Channel mute is not mapped to the MUTEC pin 1 - Channel mute is mapped to the MUTEC pin Function: Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are mapped, then the MUTEC pin is driven to the "active"...
  • Page 49 CS42426 5.22.3 FUNCTIONAL CONTROL (FUNCTIONX) Default = 00000 Function: Mute Mode - If the pin is configured as a dedicated mute pin, then the functional bits determine which channel mutes will be mapped to this pin according to the following table.

  • Page 50: Characteristics And Specifications

    3.13 5.25 Serial data port interface power 5.25 Control port interface power 5.25 °C Ambient Operating Temperature (power applied) CS42426-CQ °C CS42426-DQ ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters Symbol Units...

  • Page 51: Analog Input Characteristics

    CS42426 ANALOG INPUT CHARACTERISTICS = 25° C; VA = 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5 V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.

  • Page 52: A/D Digital Filter Characteristics

    CS42426 FILT+ Nominal Voltage Ω Output Impedance Maximum allowable DC current 0.01 0.01 Notes: 3. Typical performance numbers are taken at 25° C. Min/Max performance numbers are guaranteed across the specified temperature range, T 4. Referred to the typical full-scale voltage.

  • Page 53: Figure 20. Single Speed Mode Stopband Rejection

    CS42426 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 20. Single Speed Mode Stopband Rejection Figure 21. Single Speed Mode Transition Band 0.10...

  • Page 54: Figure 26. Double Speed Mode Transition Band (Detail)

    CS42426 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 26. Double Speed Mode Transition Band (Detail) Figure 27.

  • Page 55: Analog Output Characteristics

    CS42426 ANALOG OUTPUT CHARACTERISTICS = 25° C; VA = 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.;...

  • Page 56: D/A Digital Filter Characteristics

    CS42426 D/A DIGITAL FILTER CHARACTERISTICS Fast Roll-Off Slow Roll-Off Parameter Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz Passband (Note 10) to -0.01 dB corner 0.4535 0.4166 to -3 dB corner 0.4998 0.4998 Frequency Response 10 Hz to 20 kHz -0.01...

  • Page 57: Figure 32. Single Speed (Fast) Stopband Rejection

    CS42426 0.42 0.44 0.46 0.48 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 32. Single Speed (fast) Stopband Rejection Figure 33. Single Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.45 0.46 0.47 0.48...

  • Page 58: Figure 38. Single Speed (Slow) Transition Band (Detail)

    CS42426 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.05 0.15 0.25 0.35 0.45 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 38. Single Speed (slow) Transition Band (detail) Figure 39. Single Speed (slow) Passband Ripple 0.42...

  • Page 59: Figure 44. Double Speed (Slow) Stopband Rejection

    CS42426 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 44. Double Speed (slow) Stopband Rejection Figure 45. Double Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 0.05 0.15...

  • Page 60: Figure 50. Quad Speed (Fast) Transition Band (Detail)

    CS42426 0.15 0.05 0.05 0.15 0.05 0.15 0.25 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 50. Quad Speed (fast) Transition Band (detail) Figure 51. Quad Speed (fast) Passband Ripple Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 52.

  • Page 61: Switching Characteristics

    ADC_SCLK Rising Notes: 13. After powering up the CS42426, RST should be held low after the power supplies and clocks are settled. 14. See Table 2 on page 15 for suggested OMCK frequencies 15. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.

  • Page 62: Switching Characteristics - Control Port - I2C Format

    CS42426 SWITCHING CHARACTERISTICS - CONTROL PORT - I C FORMAT (For CQ, T = -10 to +70° C; For DQ, T = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic...

  • Page 63: Switching Characteristics - Control Port - Spi Format

    CS42426 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (For CQ, T = -10 to +70° C; For DQ, T = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;...

  • Page 64: Dc Electrical Characteristics

    CS42426 DC ELECTRICAL CHARACTERISTICS = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Parameter Symbol Units Power Supply Current normal operation, VA=5 V (Note 22) VD=5 V VD=3.3 V µA Interface current, VLC=5V (Note 23) µA...

  • Page 65: Parameter Definitions

    CS42426 7 PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal.

  • Page 66: References

    2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Con- verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Con- vention of the Audio Engineering Society, September 1997.

  • Page 67: Package Dimensions

    CS42426 9 PACKAGE DIMENSIONS 64L LQFP PACKAGE DRAWING ∝ INCHES MILLIMETERS 0.55 0.063 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 0.007 0.008 0.011 0.17 0.20 0.27 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30 0.390 0.393 BSC 0.398 9.90 10.0 BSC...

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