Cirrus Logic EP93 Series User Manual page 287

Register Descriptions
SRCPIXELSTRT
31 30 29 28
15 14 13 12
Address: 0x8004_0000 - Read/Write
Default: 0x0000_0000
Mask: 0x0000_001F
Definition: Source Pixel Start register
Bit Descriptions:
RSVD:
PEL:
DESTPIXELSTRT
31 30 29 28
15 14 13 12
Address: 0x8004_0004 - Read/Write
DS785UM1
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved - Unknown during read
Source Pixel Location - Read/Write
For the starting pixel (at the starting X-Y coordinate of the
1st scan line) of the source image for a block copy, the
value in this field specifies where the beginning bit of the
pixel is located in a 32-bit word. For example, if the
beginning bit of a 16-bit pixel is located at bit 16 of a 32-bit
word, PEL = 0x10.
The PEL field and the ADR field in the
register together define the starting pixel's address in the
SDRAM frame buffer. In REMAP mode, the starting
location written to the PEL field can be defined with bit-
level granularity. For all other modes, the granularity must
be a multiple of the pixel size: e.g. in 8 bpp mode,
acceptable PEL values are 0x00, 0x08, 0x10, and 0x18.
27 26 25 24
RSVD
11 10 9 8
RSVD
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
Graphics Accelerator
EP93xx User's Guide
19 18 17 16
3 2 1 0
PEL
"BLKSRCSTRT"
19 18 17 16
EPEL
3 2 1 0
SPEL
8-23
8