Table 3-5. Condition Code Definitions - Cirrus Logic EP93 Series User Manual

Table 3-5 shows the condition codes, which are bits [31:28] for each instruction format.
Cond Mnemonic
[31:28] Extension
0000 EQ
0001 NE
0010 CS/HS Carry Set/Unsigned Higher or Same
0011 CC/LO Carry Clear/Unsigned Lower
0100 MI
0101 PL
0110 VS
0111 VC
1000 HI
1001 LS Unsigned Lower or Same
1010 GE Signed Greater Than or Equal
1011 LT
1100 GT
1101 LE Signed Less Than or Equal
1110 AL
1111 NV
The remaining bits in the instruction formats are interpreted as follows:
• opcode1: MaverickCrunch co-processor-defined opcode
• opcode2: MaverickCrunch co-processor defined opcode
• CRn: MaverickCrunch co-processor-defined register
• CRd: MaverickCrunch co-processor-defined register
• CRm: MaverickCrunch co-processor-defined register
• Rn: Specifies an ARM base address register. These bits are ignored by the
MaverickCrunch co-processor.
• Rd: Specifies a source or destination ARM register
• cp_num: Co-processor number
• P: Pre-indexing (P=1) or post-indexing (P=0) addressing. This bit is ignored by the
MaverickCrunch co-processor.
• U: Specifies whether the supplied 8-bit offset is added to a base register (U=1) or
subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch co-
processor.
• N: Specifies the width of a data type involved in a move operation. The MaverickCrunch
DS785UM1

Table 3-5. Condition Code Definitions

Meaning
Equal
Not Equal
Minus/Negative
Plus/Positive or Zero
Overflow
No Overflow
Unsigned Higher
Signed Less Than
Signed Greater Than
Always (unconditional)
Never
Copyright 2007 Cirrus Logic
Status Flag State
C set and Z clear
C clear or Z set
N set and V set, or N clear and V clear (N = V)
N set and V clear, or N clear and V set (N ! = V)
Z clear, and either N set and V set, or N clear and V clear (Z = 0, N = V)
Z set, or N set and V clear, or N clear and V set (Z = 1, N ! = V)
MaverickCrunch Co-Processor
EP93xx User's Guide
Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
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