Table 6-2. Vicx Register Summary - Cirrus Logic EP93 Series User Manual

Vectored Interrupt Controller
EP93xx User's Guide
6
6.2 Registers
The 2 VIC blocks have an identical register definition. The offset from the respective base
address is the same:
• VIC1 Base address: 0x800B_0000
• VIC2 Base Address: 0x800C_0000
Using the ARM MMU, it is possible to remap the VIC base address to 0xFFFF_F000, giving a
lower interrupt latency.
Address
VIC base + 0000
VIC base + 0004
VIC base + 0008
VIC base + 000C
VIC base + 0010
VIC base + 0014
VIC base + 0018
VIC base + 001C
VIC base + 0020
VIC base + 0030
VIC base + 0034
VIC base + 0100
VIC base + 0104
VIC base + 0108
VIC base + 010C
VIC base + 0110
VIC base + 0114
VIC base + 0118
VIC base + 011C
VIC base + 0120
VIC base + 0124
VIC base + 0128
VIC base + 012C
VIC base + 0130
VIC base + 0134
VIC base + 0138
VIC base + 013C
VIC base + 0200
VIC base + 0204
6-8
INT_DSP ARM Core interrupt.
GPIOINTR Combined Interrupt from Any Bit in Ports A or B. See
Chapter
I2SINTR Combined Interrupt of All Sources from the I
See
Table 6-2 indicates the address offset from the base address.

Table 6-2. VICx Register Summary

Type Width Reset Value
Read 32 0x0000_0000
Read 32 0x0000_0000
Read 32
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Write 32
Read /Write 32 0x0000_0000
Read /Write 32
Read /Write 1
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 32 0x0000_0000
Read /Write 6
Read /Write 6
Copyright 2007 Cirrus Logic
28, "GPIO Interface"
2
Chapter 21, "I S Controller"
Name
VICxIRQStatus
VICxFIQStatus
- VICxRawIntr
VICxIntSelect
VICxIntEnable
- VICxIntEnClear
VICxSoftInt
- VICxSoftIntClear
0x0 VICxProtection
VICxVectAddr
VICxDefVectAddr
VICxVectAddr0
VICxVectAddr1,
VICxVectAddr2,
VICxVectAddr3,
VICxVectAddr4,
VICxVectAddr5,
VICxVectAddr6
VICxVectAddr7,
VICxVectAddr8,
VICxVectAdd9,
VICxVectAddr10,
VICxVectAddr11,
VICxVectAdd12,
VICxVectAddr13,
VICxVectAddr14,
VICxVectAddr15
0x00 VICxVectCntl0,
0x00 VICxVectCntl1,
2
S Controller.
Description
IRQ status register
FIQ status register
Raw interrupt status register
Interrupt select register
Interrupt enable register
Interrupt enable clear register
Software interrupt register
Software interrupt clear register
Protection enable register
Vector address register
Default vector address register
Vector address 0 register
Vector address 1 register
Vector address 2 register
Vector address 3 register
Vector address 4 register
Vector address 5 register
Vector address 6 register
Vector address 7 register
Vector address 8 register
Vector address 9 register
Vector address 10 register
Vector address 11 register
Vector address 12 register
Vector address 13 register
Vector address 14 register
Vector address 15 register
Vector control 0 register
Vector control 1 register
DS785UM1