Cirrus Logic EP93 Series User Manual page 674

2
I S Controller
EP93xx User's Guide
Default:
Definition:
Bit Descriptions:
21
I2STX1En
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
I2STX2En
31 30
15 14
Address:
Default:
21-18
0x0000_0000
TX0 Channel Enable
RSVD:
i2s_tx0_EN:
29 28 27 26
13 12 11 10
0x8082_0038 - Read/Write
0x0000_0000
TX1 Channel Enable
RSVD:
i2s_tx1_EN:
29 28 27 26
13 12 11 10
0x8082_003C - Read/Write
0x0000_0000
Reserved. Unknown During Read.
TX0 Channel Enable
25 24 23 22
RSVD
9 8 7 6
RSVD
Reserved. Unknown During Read.
TX1 Channel Enable
25 24 23 22
RSVD
9 8 7 6
RSVD
Copyright 2007 Cirrus Logic
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
i2s_tx1_EN
17 16
1 0
i2s_tx2_EN
DS785UM1