Video Fifo; Figure 7-2. Video Buffer Diagram - Cirrus Logic EP93 Series User Manual

register, "VidScrnPage" on page
corner of the lower half of the display begins at the word address stored in the
"VidScrnHPage"
load address counters at the beginning of the video frame.
The VILOSATI continues to service the video FIFO until it has transferred an entire screen
image from memory. The size of the screen image is controlled by the values stored in the
"ScrnLines" and
displayed (active) lines for the video frame. The
words for each displayed (active) video line. A separate register,
defines the word offset in memory between the beginning of each line and the next line.
Setting the VLineStep value larger than the LineLength value provides the capability for
image panning as shown in

7.4.2 Video FIFO

The video FIFO is used to buffer data transferred from the image memory to the Video output
circuitry without stalling the video data stream. The FIFO consists of a dual port RAM with
input and output index counters and control circuitry to operate it as a FIFO memory. The
input data bus width to the FIFO is 32 bits. During half page mode, when the display requires
scan out of the bottom and top half of the screen at the same time (dual scan), top half (or
bottom half) data is stored in every other FIFO location.
When the screen is single scan (scanned out as a single progressive image), FIFO data is
stored sequentially. The FIFO output data bus is 64 bits wide and can output even and odd
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
7-46. For a dual scan display, information from the upper left
register. The "VidScrnPage"
"LineLength" registers. The
Figure 7-2.
Displayed Portion
VIDSCRNPAGE
start address
VIDSCRHPG
start address
(Dual Scan mode only)
LINELENGTH + 1

Figure 7-2. Video Buffer Diagram

Copyright 2007 Cirrus Logic
and "VidScrnHPage"
"ScrnLines" register defines the total number of
"LineLength" register defines the number of
Frame Buffer
VLINESTEP
EP93xx User's Guide
registers are used to pre-
"VLineStep" on page 7-48,
7
7-9