Cirrus Logic EP93 Series User Manual page 364

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
9
GlIntSts
31 30
15 14
INT
Address:
Chip Reset:
Soft Reset:
9-62
RxROI:
MIIII:
PHYI:
TI:
AHBE:
OTHER:
TxSQ:
RxSQ:
29 28 27 26
13 12 11 10
0x8001_0060 - Read/Write
0x0000_0000
0x0000_0000
Copyright 2007 Cirrus Logic
When a runt frame is received with a CRC error, the
RxRuntCnt register is incremented, when the MSB of the
count is set, the RuntOv bit is set in the Interrupt Status
Register. If the RxROIE bit is set, an interrupt will be
generated.
The MII Status bit is set whenever a management
operation on the MII bus is completed.
The PHY Status bit is set when the MAC detects a change
of status event in the PHY.
The Timeout bit is set when the general timer (GT) count
register reaches zero.
This bit is set if a MAC generated AHB cycle terminated
abnormally. The Queue ID bits (Bus Master Status) will
indicate the DMA Queue which was active when the abort
occurred. DMA operation is halted on all queues until this
bit is cleared, and the queues are restarted via the Bus
Master Control register.
This bit is set when a status other than that covered by bits
10, 3 and 2 is present.
This bit is set when a status affecting the transmit status
queue has been posted.
This bit is set when a status affecting the receive status
queue has been posted. This bit can only be set if bit 2
(REOFIE), bit 1 (REOBIE) and bit 0 (RHDRIE) of the
Interrupt Enable (IntEn) register are set (enabled).
25 24 23 22
RSVD
9 8 7 6
RSVD
21 20 19 18
5 4 3 2
17 16
1 0
DS785UM1