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Cirrus Logic Crystal CS98000 Series Manual

Internet dvd (idvd) chip solution
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Internet DVD (iDVD) Chip Solution
Features
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Powerful Dual 32-bit RISCs >160MIPS
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Software based on popular RTOS, C/C++
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MPEG video decoder supports DVD, VCD,
VCD 3.0, SVCD standards
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Video input with picture-in-picture & zoom
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8-bit multi-region OSD w/vertical flicker filter
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Universal subpicture unit for DVD and SVCD
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PAL<->NTSC Scaling ~ Transcoding
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Supports SDRAM and FLASH memories
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Powerful 32-bit Audio DSP >80 MIPS
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Decodes: 5.1 channel AC-3, MPEG Stereo
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Plays MP-3 CDs (a MP-3 CD =12 albums)
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Karaoke echo mix and pitch shift
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Optional 3-D Virtual, bass & treble control
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8-channel dual-zone PCM output
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IEC-60958/61937 Out: AC-3, DTS, MPEG
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Multi-Mode Serial Audio I/O: I2S & AC-Link
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AV Bus or ATAPI interface or DVD/CD/HD
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GPIO support for all common sub-circuits
I-Cache
MMU
Filter
MPEG Decoder
VLC Parser
RAM
Video Processor
On-Screen Display
Picture-in-Picture
Video/Graphics Display
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
RISC-1
RISC-2
D-Cache
I-Cache
MAC
MMU
Video Input
Clock Manager
Scaler
Dataflow Engine
IDCT
DMA / BitBlit
MoCo
SRAM Buffer
External I/Os
Remote Input
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Description
Overall the CS98000 Crystal DVD Processor is targeted
as a market specific consumer entertainment processor
empowering new product classes with the inclusion of a
DVD player as a fundamental feature. This integrated
circuit when used with all the other Crystal mixed signal
data converters, DSPs and high quality factory firmware
enables the conception and rapid design of market lead-
ing internet age products like:
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DVD A/V Mini-System
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Home Media Controller
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Combination DVD Player
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Car/SUV Entertainment Unit
Future Firmware Enhancements:
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Web I/O via AC-Link Input & Built-in Soft Modem
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DVD Audio Navigation
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MLP Decoder, DTS Decoder, AAC Decoder
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MP-3 Encoder, Ripping Controller
ORDERING INFORMATION
CS98000-CQ
CS98010-CQ
Memory Controller
D-Cache
SDRAM Control
MAC
FLASH Control
Subpicture Decode
Scaler
System Controls
STC
Interrupts
Registers
GPIOs
SDRAM
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
CS98000
0° to 70° C
208-pin
0° to 70° C
128-pin
32- Bit DSP
I-Cache
X,Y Data
Memory
CPU / MAC
Audio I/O
PCM Out
PCM In
XMT958
A/V Bus
ATAPI-IDE
Local Bus
DS525PP1
DEC '00
1

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  • Page 1 SDRAM Local Bus This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2000 DEC ‘00 P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)

  • Page 2: Table Of Contents

    (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture...
  • Page 3 CS98000 4. MEMORY MAP ........................15 4.1 Processor Memory Map ....................15 4.2 Host Port Memory Map ....................15 4.3 Internal IO Space Map ..................... 15 5. REGISTER DESCRIPTION ....................16 5.1 CS98000 Register Space ....................16 6. PIN DESCRIPTION ......................... 25 6.1 Pin Assignments ......................

  • Page 4: Characteristics And Specifications

    CS98000 CHARACTERISTICS AND SPECIFICATIONS AC Electrical Specifications 1.1.1 ATAPI Interface CS98000 can interface with ATAPI-type slave loader gluelessly. Figure 1 illustrates a read ATAPI trans- action and a write ATAPI transaction. PIO mode 4 is implemented for sufficient data transfer rate between ATAPI device and CS98000.

  • Page 5: Sdram Interface

    CS98000 1.1.2 SDRAM Interface CS98000 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure 2 shows the refresh cycle performed by CS98000. Figure 3 shows a burst read (length = 8) transaction, while Figure 4 shows a burst write (length = 8) transaction. Figure 5 and the following table show detailed timing. In both Figure 3 and 4, CAS latency is programmed to 3.

  • Page 6: Sdram Timing

    CS98000 mper CLOCK MRAS,MCAS MWE,AP,DQM0-3 MCKE,MA-011 mdow DQ0-DQ31(WRITE) DQ0-DQ31(READ) msur msuw Figure 5. SDRAM Timing Symbol Description Unit tmsur Input to Clock Setup tmhr Input to Clock Hold tmco Clock to Out tcch Clk High Time tccl Clk Low Time tmper Clk Period 12.2...

  • Page 7: Video Interface

    CS98000 1.1.3 Video Interface Figure 6 illustrates the CS98000 interfaces with standard video encoder. CS98000 WITH VIDEO ENCODER Symbol Description Unit Tdsu Video data setup time Video data hold time Tsysu HSYNC or VSYNC to Clock setup time Tsyh Clock to HSYNC or VSYNC hold time Tckl Video clock low time 14.8...

  • Page 8: Dc Electrical Specification

    CS98000 DC Electrical Specification ABSOLUTE MAXIMUM RATING Symbol Description Unit Power Supply Voltage on I/O ring -0,5 Volts Power Supply Voltage on core logic and PLL -0.5 Volts CORE Digital Input Applied Voltage (power applied) -0.5 Volts Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature Vapor Phase Soldering Temperature...

  • Page 9: Typical Application

    CS98000 2. TYPICAL APPLICATION The Figure 7 shows a typical example of a complete internet-DVD solution using the CS98000. Phone Remote Line Keyboard/ Control CODEC Parallel Port Front Panel Audio-L(3) (3)Audio Audio-L Audio CS98000 DACs Audio-R(3) Audio-R Driver Video Video S/PDIF Decoder Video...

  • Page 10: Functional Description

    CS98000 3. FUNCTIONAL DESCRIPTION 3.2.2 DSP-32 • Powerful 24/32 bit DSP processor Block Diagram • 24 bit fixed point logic, with 54 bit accumula- The CS98000 block is shown in Figure 8. tor. CS98000 Device Details • Single-cycle throughput, 2 cycle latency multi- 3.2.1 RISC-32 ply accumulate, 32 bit simple integer logic.

  • Page 11: Memory Controller

    CS98000 • Both hardware and software interrupts on data 3.2.8 Audio Interface or debug • Supports PCM, I S and IEC-958 outputs at up • Performance monitors which measures DRAM to 96 KHz output rate. bandwidth, usage, and RSK performance •...

  • Page 12: Sub-Picture Processor

    CS98000 • Supports 4:2:0, 4:2:2, YUV655, RGB565 and MIPS R3000. In addition to the standard MIPS RGB555 frame buffer inputs. R3000 instruction code, the RISC processor also has a MAC engine, which performs multiply/accu- • High quality scaling using a vertical and a hor- mulate in 2 cycles in a pipelined fashion with C izontal 16 taps polyphase programmable filter, support,...

  • Page 13: Dataflow Control (Dma)

    CS98000 Sharing the same interface, CS98000 also supports ble. Internal PLLs are used to generate the internal flash ROM, OTP, or mask ROM interface. Code is system and memory clocks, and audio clocks of stored in ROM. After system is booted, the code is any widely used frequency.

  • Page 14: Audio Processing

    4:2:0, 4:2:2, YUV655, RGB565 The DMA and decompression stages of audio pro- and RGB555. Cirrus Logic provides some easy to cessing can be done with a combination of the use utilities in order to get the best advantage of the DMA unit, DSP and RISC processors.

  • Page 15: Memory Map

    CS98000 4. MEMORY MAP Host Port Memory Map Table 1 lists the memory map as viewed by host Processor Memory Map slave port. The CS98000 externally supports up to 32 Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table lists Internal IO Space Map the memory map as viewed by the RISC proces- Table 2 shows how the Internal IO space is mapped sors, and identifies whether each segment is...

  • Page 16: Register Description

    CS98000 5. REGISTER DESCRIPTION Table 4 lists all the registers for the CS98000 and their addresses, and indicates whether the registers CS98000 Register Space are read/write (R/W), read only (RO) or write only Table 3 lists the register groups, and how they are (WO).
  • Page 17 CS98000 General Semiphore_Register_7 General GenIO_Read_Data General GenIO_Write_Data General GenIO_Tri_State_Enable General GenIO_Positive_Edge General GenIO_Negative_Edge General GenIO_Interrupt_Status General GenIO_Positive_Edge_Mask General GenIO_Negative_Edge_Mask General GenIO_Level_Mask General GenIO_Mode Register 1040 General GenIOMIS_Read_Data 1044 General GenIOMIS_Write_Data 1048 General GenIOMIS_Tri_State_Enable 104C General GenIOMIS_Positive_Edge 1050 General GenIOMIS_Negative_Edge 1054 General GenIOMIS_Interrupt_Status 1058...
  • Page 18 CS98000 General RSK0_Interrupt_Mask2 General RSK0_Interrupt_Set2 General RSK0_Interrupt2_Status General RSK0_Interrupt_Cause2 1080 General RSK1_Interrupt_Mask 1084 General RSK1_Interrupt_Set 1088 General RSK1_Interrupt_Status 108C General RSK1_Interrupt_Cause 10A0 General RSK1_Interrupt_Mask2 10A4 General RSK1_Interrupt_Set2 10A8 General RSK1_Interrupt2_Status 10AC General RSK1_Interrupt_Cause2 General DSP_Interrupt_Mask2 General DSP_Interrupt_Set2 General DSP_Interrupt2_Status General DSP_Interrupt_Cause2 General Timer_0...
  • Page 19 CS98000 Host Stream_Transfer_Size Host DRAM_Burst_Threshold Host Host_Master_Control Dram controller DRAM_Controller_Priority0 Dram controller DRAM_Controller_Priority1 Dram controller DRAM_Controller_Priority2 Dram controller DRAM_Controller_Priority3 Dram controller DRAM_Controller_Priority4 Dram controller DRAM_Controller_Setup Dram controller DRAM_Command Dram controller DRAM_Controller_Mb_Width Dram controller DRAM_Controller_Debug_Control Dram controller DRAM_Debug_Status DMA_Enable DMA_Control DMA_Status Xfer_Byte_Cnt Dram_Byte_Start_Addr Sram_Byte_Start_Addr...
  • Page 20 CS98000 SER/DCI DCI_Mbytes_Switch SER/DCI DCI_Diagnostic SER/DCI DCI_Active SER/DCI Serial_Frame_Sync_Control SER/DCI Serial_Output_Input_Control SER/DCI AC97_Codec_Control SER/DCI AC97_Codec_Command SER/DCI Serial_Output_Fifo_Start_Address SER/DCI Serial_Output_Fifo_End_Address SER/DCI Serial_Input_Fifo_Start_Address SER/DCI Serial_Input_Fifo_End_Address SER/DCI Serial_Output_Fifo_Read_Address SER/DCI Serial_Input_Fifo_Write_Address SER/DCI Serial_Clock_Synthesis_Parameters SER/DCI Codec_Register_Status SER/DCI Slot5_Register_Data SER/DCI Slot10_Register_Data SER/DCI Slot11_Register_Data SER/DCI Slot12_Register_Data SER/DCI Out_fifo_int SER/DCI In_fifo_int...
  • Page 21 CS98000 Sync Control Highlight_Start_PTS Sync Control Highlight_End_PTS Sync Control Button_End_PTS Sync Control Highlight_Control_Information_Address Sync Control Video_PTS Sync Control Audio_PTS Sync Control Subpicture_PTS Sync Control Audio_Time Sync Control Video_Sync_Debug Sync Control SP_DRC_VPTS_Debug Sync Control Frame_Count_Interrupt Sync Control Video_DTS Sync Control Sync_Interrupt_Status Sync Control Sync_Interrupt_Control Sync Control...
  • Page 22 CS98000 VIS_EndY VIS_Frame_Base VIS_U_Offset VIS_V_Offset VIS_Frame_Size PIP_Control PIP_VidBrdStartX PIP_VidBrdEndX PIP_VidBrdStartY PIP_VidBrdEndY PIP_BorderClr PIP_Vscale PIP_Line_Offnum_Bot PIP_FrBaseY PIP_FrBaseU PIP_FrBaseV PIP_Line_Width PIP_ Line_Offnum_Top PIP_Frame_Size Video Processor Video_Processor_Control Video Processor Video_DRAM_Line_Length Video Processor Display_ActiveX Video Processor Display_ActiveY Video Processor Blank_Color Video Processor Internal_Hsync_Count Video Processor Internal_Vsync_Count Video Processor Horizontal_Y_Offset...
  • Page 23 CS98000 Video Processor Anti-Flicker Video Processor Gamma Control Video Processor Gamma Control Video Processor Gamma Control Video Processor Gamma Control Video Processor Gamma Control Video Processor Gamma Control Video Processor Gamma Control Video Processor Gamma Control Video Processor Vid_Sync Adjust Subpicture Subpicture_Color0 Subpicture...
  • Page 24 CS98000 On Screen Display OSD_Region2_Vlimits On Screen Display OSD_Region2_DramBase On Screen Display OSD_Region3_Control On Screen Display OSD_Region3_Hlimits On Screen Display OSD_Region3_Vlimits On Screen Display OSD_Region3_DramBase On Screen Display OSD_Blend On Screen Display OSD_Debug1 On Screen Display OSD_Debug2 PCM_Run_Clear PCM_Output_Control PCM_Out_FIFO_Start_Address PCM_Out_FIFO_End_Address PCM_Out_FIFO_Interrupt_Address PCM_Out_FIFO_Current_Address...

  • Page 25: Pin Description

    CS98000 6. PIN DESCRIPTION H_D_[15:0] M_A_[11:0] H_CS_[3:0] M_BS_L H_A_[4:0] M_D_[31:0] H_ALE M_DQM_[3:0] Host/Loader H_RD M_RAS_L Memory IF H_WR M_CAS_L (30) (57) H_CKO M_WE_L H_RDY M_AP M_CKE M_CKO VIN_D[7:0] NVR_OE_L VIN_HSNC Video In NVR_WR_L VIN_VSNC CS98000 (12) VIN_CLK HSYNC VIN_FLD Video out VSYNC CLK27_O (11)

  • Page 26: Pin Assignments

    CS98000 Pin Assignments pins. For some signal pins, a secondary function and direction are also shown. For pins having more Table 6 lists the pin number, pin name and pin type than one function, the primary function is chosen for the 208 pin CS98000 package. The primary when the chip is reset.
  • Page 27 CS98000 VSS_CORE Core Ground M_D_7 SDRAM Data[7] ROM/NVRAM Data[7] VDD_IO I/O Power 3.3V GPIO_D2 GenioDVD[2] M_D_9 SDRAM Data[9] ROM/NVRAM Data[9] VDD_CORE Core Power 2.5V M_D_6 SDRAM Data[6] ROM/NVRAM Data[6] GPIO_D3 GenioDVD[3] M_D_10 SDRAM Data[10] ROM/NVRAM Data[10] M_D_5 SDRAM Data[5] ROM/NVRAM Data[5] M_D_11 SDRAM Data[11] ROM/NVRAM Data[11]...
  • Page 28 CS98000 GPIO_D8 GenioDVD[8] M_D_19 SDRAM Data[19] ROM/NVRAM Address[15] M_D_29 SDRAM Data[29] M_D_18 SDRAM Data[18] ROM/NVRAM Address[14] NV_WE_L NVRAM Write Enable GenioMis[8] VSS_CORE Core Ground M_D_30 SDRAM Data[30] ROM/NVRAM Decode Low VDD_CORE Core Power 2.5V H_ALE Host Address Latch GenioHst[13] M_D_17 SDRAM Data[18] ROM/NVRAM Address[13] M_D_31...
  • Page 29 CS98000 H_D_9 Host Data[9] DVD Control Ready 1, 2 H_D_8 Host Data[8] DVD Control Clock 1, 2 VSS_IO I/O Ground H_CKO Host Clock GenioHst[19] H_D_7 Host Data[7] DVD Data[7] H_D_6 Host Data[6] DVD Data[6] H_D_5 Host Data[5] DVD Data[5] AUD_BCK Audio Out Bit Clock GenioMis[3] H_D_4...
  • Page 30 CS98000 VSS_CORE Core Ground HSYNC Video Output Hsync GenioMis[4] VIN_HSYNC Video Input Hsync GenioMis[24] VDD_CORE Core Power 2.5V VSYNC Video Output Vsync GenioMis[5] VDAT_0 Video Output Data[0] VIN_D0 Video Input Data[0] GenioMis[16] VDAT_1 Video Output Data[1] VDAT_2 Video Output Data[2] VDAT_3 Video Output Data[3] VIN_D1...

  • Page 31: Miscellaneous Interface Pins

    CS98000 GPIO_15 General Purpose IO[15] VSS_CORE Core Ground IR_IN Infrared input XTLCLOCK 27 MHz Clock In VDD_CORE Core Power 2.5V SPDIF_O S/PDIF Out RST_N Reset In MFG_TEST (Tie to ground) VIN_FLD Video Input Field VSS_PLL PLL Ground Table 6. Pin assignments (Continued) Notes: 1.

  • Page 32: Table 8. Sdram Interface

    CS98000 Signal Name Type Description 87, 83, 79, 76, M_D[31..0] Memory Data Bus. CS98000 can use all 32 bits or can use 74, 71, 68, 64, only M_D[15..0], in which case M_D[31..16] can be left un-con- 67, 70, 72, 75, nected.

  • Page 33: Video Output Interface

    CS98000 Video Output Interface be the sync master. In this case, the HSYNC and VSYNC pins can be redefined as GPIOs. This is the interface to a video encoder chip that will send the CS98000 video signals to a TV. The Video Input Interface output format is either CCIR-601 or CCIR-656.

  • Page 34: Audio Output/Input Interface

    CS98000 Audio Output/Input Interface AC97/CODEC Interface This is the audio PCM interface that connects to an This serial interface could be used either as a sec- audio CODEC. The sample rate and the size of the ond PCM CODEC interface or as an AC97 serial samples are programmable for both input and out- link to an AC97 compliant CODEC.

  • Page 35: Host Master/Atapi Interface

    CS98000 Host Master/ATAPI Interface 6.12 Power and Ground This 16 bits parallel host interface allows the The CS98000 requires 3 different types of power CS98000 to be a host master, controlling other de- supplies – PLLs, internal logic and IO pins -. The vices that would be used on the same system.

  • Page 36: Table 15. Dvd I/O Channel Interface

    CS98000 Signal Name Type Description 121, 122, 123, H_D[7:0] DVD_Data[7:0] – DVD data port parallel data input from 125, 127, 130, loader 132, 134 H_D[8] Control port clock to loader H_D[9] Control port ready signal from loader H_D[10] Control port serial command to loader H_D[11] Control port serial status from loader H_D[12]...

  • Page 37: Table 17. Power And Ground

    CS98000 Signal Name Type Description 1, 105, 158 VDD_PLL 2.5V for internal PLLs 41, 66, 84, 108, VDD_CORE 2.5V for internal core logic 129, 141, 161, 178, 203 20, 38, 91, 131, VDD_IO 3.3V for I/O’s 104, 157, 208 VSS_PLL Ground for internal PLLs 36, 63, 82, 103, VSS_CORE...

  • Page 38: Package Specifications

    CS98000 7. PACKAGE SPECIFICATIONS 30.6 ±0.2 28.00 ±0.05 3.80(MAX) 3.35 ±0.05 0.35 ±0.1 0.50±0.05 0.22±0.05 Detail A 15° 0°(MIN) R0.15 (MIN) R0.20 10° WITH PLATING 0.50±0.1 5° BASE METAL 0.20 1.3±0.1 DETAIL A DS525PP1...
  • Page 39 • Notes •...

This manual is also suitable for:

Crystal cs98000-cqCrystal cs98010-cq

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