Load And Store Instructions; Table 3-11. Mnemonic Codes For Loading Floating Point Value From Memory - Cirrus Logic EP93 Series User Manual

Maverick
ARM
Crunch
Co-
Co-
Processor
Processor
Instruction
Instruction
Type
Type
64-bit integer
CDP
arithmetic
Accumulator
CDP
arithmetic

3.5.1 Load and Store Instructions

Loading Floating Point Value from Memory
31:28 27:25 24
cond 1 1 0 P
Description:
Loads a single or double precision floating point value from memory into
MaverickCrunch register.

Table 3-11. Mnemonic Codes for Loading Floating Point Value from Memory

CFLDRS<cond> CRd, [Rn, <offset>]{!}
CFLDRS<cond> CRd, [Rn], <offset>
CFLDRD<cond> CRd, [Rn, <offset>]{!}
CFLDRD<cond> CRd, [Rn], <offset>
DS785UM1
Table 3-10. MaverickCrunch Instruction Set (Continued)
Instruction
cfabs64 CRd, CRn CRd gets absolute value of CRn
cfneg64 CRd, CRn CRd gets negation of CRn
cfadd64 CRd, CRn,
CRd gets sum of CRn and CRm
CRm
cfsub64 CRd, CRn,
CRd gets CRn minus CRm
CRm
cfmul64 CRd, CRn,
CRd gets the product of CRn and CRm
CRm
cfmadd32 CRa, CRd,
Accumulator CRa gets sum of CRd and the product of CRn and CRm
CRn, CRm
cfmsub32 CRa, CRd,
Accumulator CRa gets CRd minus the product of CRn and CRm
CRn, CRm
cfmadda32 CRa, CRd, Accumulator CRa gets sum of accumulator CRd and the product of CRn
CRn, CRm and CRm
cfmsuba32 CRa, CRd, Accumulator CRa gets accumulator CRd minus the product of CRn and
CRn, CRm CRm
23 22 21 20 19:16
U N W 1
Mnemonic
Copyright 2007 Cirrus Logic
Description
15:12 11:8
Rn CRd 0 1 0 0
Addressing Mode
Immediate pre-indexed
Immediate post-indexed
Immediate pre-indexed
Immediate post-indexed
MaverickCrunch Co-Processor
EP93xx User's Guide
7:0
8_bit_word_offset
N
0
0
1
1
3
3-21