Ahb Implementation Details; Figure 2-2. Typical Amba Ahb System - Cirrus Logic EP93 Series User Manual

• Latched address and control
• A simple Interface to on-chip peripherals such as UARTs and AC'97.

2.2.6 AHB Implementation Details

Peripherals or the external memory interface that have high bandwidth and low latency
requirements are connected to the CPU using the AHB bus. The peripherals include the
Vectored Interrupt Controllers (VIC1, VIC2), DMA, LCD/Raster registers, USB host, IDE,
Ethernet MAC and the bridge to the APB interface. The AHB/APB Bridge transparently
converts the AHB accesses into the slower speed APB accesses. All of the control registers
for the APB peripherals are programmed using the AHB/APB bridge interface. The main AHB
data and address lines are configured using a multiplexed bus. This removes the need for
three state buffers and bus holders, and simplifies bus arbitration.
shows the main data paths in the processor's AHB implementation.
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Figure 2-2. Typical AMBA AHB System

Copyright 2007 Cirrus Logic
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