Cirrus Logic EP93 Series User Manual page 710

AC'97 Controller
EP93xx User's Guide
AC97Reset
31 30
15 14
22
Address:
Definition:
Bit Descriptions:
22-22
29 28 27 26
13 12 11 10
RSVD
0x8088_00A0 - Read/Write
Controller Reset Register. The AC'97 Controller RESET register is a
read/write register that controls various functions within the AC'97 Controller
of the RESET port. All the register bits are cleared to "0" when reset.
RSVD:
EFORCER:
FORCEDRESET: If the EFORCER bit is set to "1", the RESET port will follow
TIMEDRESET:
Copyright 2007 Cirrus Logic
25 24 23 22
9 8 7 6
Reserved. Unknown During Read.
Enable for the Forced RESET bit.
1 - FORCEDRESET become active
0 - FORCEDRESET has no effect.
whatever value is written to this bit. If this mechanism is
used to control the RESET port, it is up to software to
ensure that the signal is high long enough to meet the
specification of the external device.
This bit has priority over the TIMEDRESET bit.
If this bit is set to "1", the RESET port is forced to "0" for
five pulses of the 2.9491 MHz clock
(0.339 µs x 5 = 1.695 µs maximum reset pulse and
1.356 µs minimum reset pulse using this 2.9491 MHz
clock). After which this bit is zeroed.
21 20 19 18
5 4 3 2
EFORCER
17 16
1 0
FORCED TIMED
RESET RESET
DS785UM1