Cirrus Logic EP93 Series User Manual

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EP93XX

ARM

9 Embedded Processor Family

EP93xx

Use r 's Gu id e

SEP 2007

DS785UM1

http://www.cirrus.com

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Summary of Contents for Cirrus Logic EP93 Series

Page 2 Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Page 3: Table Of Contents
P.2 Related Documents from Cirrus Logic ........
Page 4 4.2 Boot Options ............. . .4-4 4.2.1 UART Boot ........................4-6 4.2.2 SPI Boot ..........................4-6 4.2.3 FLASH Boot........................4-6 4.2.4 SDRAM or SyncFLASH Boot ..................4-7 © Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 5 7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays ....7-15 7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters ............7-16 7.4.8.2 VERT_CNT3, VERT_CNT4 Counters ............7-16 7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters ...........7-16 7.4.8.4 HORZ_CNTx (pixel) timing ................7-16 7.4.8.5 VERT_CNTx (line) timing ................7-16 © DS785UM1 Copyright 2007 Cirrus Logic, Inc.
Page 6 8.6 Register Usage .............8-13 8.6.1 Breshenham’s Algorithm Line Draw ................8-13 8.6.2 Example of Breshenham’s Algorithm Line Draw ............8-15 8.6.3 Block Fill Function ......................8-16 © Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 8 11.2.1 Data Transfer Types....................11-2 11.2.2 Host Controller Interface....................11-3 11.2.2.1 Communication Channels................11-3 11.2.2.2 Data Structures..................11-4 11.2.3 Host Controller Driver Responsibilities ................11-6 11.2.3.1 Host Controller Management..............11-6 11.2.3.2 Bandwidth Allocation .................11-6 11.2.3.3 List Management ..................11-7 11.2.3.4 Root Hub....................11-7 © viii Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 9 14.2.1 UART Functional Description ..................14-2 14.2.1.1 AMBA APB Interface .................14-2 14.2.1.2 DMA Block ....................14-2 14.2.1.3 Register Block....................14-2 14.2.1.4 Baud Rate Generator.................14-4 14.2.1.5 Transmit FIFO....................14-4 14.2.1.6 Receive FIFO.....................14-4 14.2.1.7 Transmit Logic ...................14-4 14.2.1.8 Receive Logic ....................14-4 © DS785UM1 Copyright 2007 Cirrus Logic, Inc.
Page 14 Figure 1-3. EP9307 Block Diagram .......................1-3 Figure 1-4. EP9312 Block Diagram .......................1-4 Figure 1-5. EP9315 Block Diagram .......................1-4 Figure 2-1. ARM920T Block Diagram ......................2-2 Figure 2-2. Typical AMBA AHB System ......................2-7 Figure 2-3. Main Data Paths .........................2-8 © Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 15 Figure 9-16. Transmit Flow Diagram ......................9-34 Figure 9-17. Transmit Descriptor Data/Status Flow ..................9-36 Figure 10-1. DMA M2P/P2M Finite State Machine ..................10-7 Figure 10-2. M2M DMA Control Finite State Machine................10-10 Figure 10-3. M2M DMA Buffer Finite State Machine.................10-12 © DS785UM1 Copyright 2007 Cirrus Logic, Inc.
Page 16 Figure 23-9. Microwire Frame Format (Single Transfer) ................23-10 Figure 23-10. Microwire Frame Format (Continuous Transfers) ...............23-12 Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements ......23-12 Figure 24-1. PWM_INV Example ........................24-6 © Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 17 Table 3-1. Saturation for Non-accumulator Instructions................3-5 Table 3-2. Accumulator Bit Formats for Saturation ..................3-5 Table 3-3. Comparison Relationships and Their Results ................3-7 Table 3-4. ARM® Condition Codes and Crunch Compare Results...............3-7 Table 3-5. Condition Code Definitions......................3-15 © DS785UM1 Copyright 2007 Cirrus Logic, Inc. xvii...
Page 18 Table 7-14. Blink Mode Definition Table .....................7-58 Table 7-15. Output Shift Mode Table ......................7-59 Table 7-16. Bits per Pixel Scanned Out ......................7-59 Table 7-17. Grayscale Look-Up-Table (LUT) ....................7-75 Table 8-1. Screen Pixels ..........................8-4 © xviii Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 19 Table 10-6. PPALLOC Register Bits Decode for a Receive Channel ............10-24 Table 10-7. PPALLOC Register Reset Values..................10-24 Table 10-8. PPALLOC Register Reset Values..................10-30 Table 10-9. BWC Decode Values ......................10-33 Table 10-10. DMA Global Interrupt (DMAGlInt) Register ................10-45 © DS785UM1 Copyright 2007 Cirrus Logic, Inc.
Page 20 Table 16-2. DeviceCfg Register Bit Functions ....................16-2 Table 17-1. Bit Values to Select Ir Module ....................17-3 Table 17-2. Address Offsets for End-of-Frame Data...................17-5 Table 17-3. MIR Frame Format........................17-9 Table 17-4. DeviceCfg.IonU2 Pin Function ....................17-20 © Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 21 Table 28-1. EP9301 and EP9302 GPIO Port to Pin Map................28-6 Table 28-2. EP9307 GPIO Port to Pin Map....................28-6 Table 28-3. EP9312 GPIO Port to Pin Map....................28-7 Table 28-4. EP9315 GPIO Port to Pin Map....................28-8 © DS785UM1 Copyright 2007 Cirrus Logic, Inc.
Page 22 EP93xx family. New content has been added, formatting 2007 improved, and all known documentation errors fixed. Please discard previous User’s Guides and rely on this manual for your future reference needs. © xxii Copyright 2007 Cirrus Logic, Inc. DS785UM1...
Page 23: Preface
Table P-2. Chapter Number and Function, Applicable EP93xx Processor Chapter Number and Function Applicable EP93xx Processor EP9301 EP9302 EP9307 EP9312 EP9315 0: Preface 1: Introduction 2: ARM920T Core and Advanced High-Speed Bus 3: MaverickCrunch Co-processor 4: Boot ROM 5: System Controller DS785UM1 Copyright 2007 Cirrus Logic...
Page 24 23: Synchronous Serial Port 24: Pulse Width Modulators 25: Analog Touch Screen Interface/ADC 5-ADC 5-ADC 8-Wire TS 8-Wire TS 8-Wire TS 26: Keypad Interface 27: IDE Interface 2 Devices 2 Devices 28: GPIO Interface 29: Security 30: Glossary DS785UM1 Copyright 2007 Cirrus Logic...
Page 25: Related Documents From Cirrus Logic
EP93xx User’s Guide Note: “X” means Function is included; “-” means Function is not included P.2 Related Documents from Cirrus Logic 1. EP9301 Data Sheet, Document Number - DS636PP5 2. EP9302 Data Sheet, Document Number - DS653PP3 3. EP9307 Data Sheet, Document Number - DS667PP4 4.
Page 26: Register Example
RSVD RSVD SBOOT LCSn7 LCSn6 LASDO LEEDA LEECLK RSVD LCSn2 LCSn1 Address: 0x8093_009C - Read/Write, Software locked Default: 0x0000_0000 Definition: System Configuration Register. Provides various system configuration options. Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 Copyright 2007 Cirrus Logic...
Page 27 Latched version of EEDAT pin. LEECLK: Define Internal or external boot: Internal External LCSn1, LCSn2: Define Watchdog startup action: Watchdog disabled, Reset duration disabled Watchdog disabled, Reset duration active Watchdog active, Reset duration disabled Watchdog active, Reset duration active DS785UM1 Copyright 2007 Cirrus Logic...
Page 29: Chapter 1. Introduction
200 MHz 100 MHz 352 PBGA Features of the EP93xx processors are summarized in Table 1-2. Block diagrams are shown Figure 1-1 EP9301, Figure 1-2 EP9302, Figure 1-3 EP9307, Figure 1-4 EP9312, and Figure 1-5 EP9315. DS785UM1 Copyright 2007 Cirrus Logic...
Page 30: Figure 1-1. Ep9301 Block Diagram
JTAG AC’97 Memory Management Unit 2 USB 2.0 FS Host RTC with SW Trim Boot ROM High-Speed Bus (AHB) Watchdog Timer Vectored Inerrupts AHB/APB Bridge 4 Timers Peripheral Bus (APB) Figure 1-1. EP9301 Block Diagram DS785UM1 Copyright 2007 Cirrus Logic...
Page 31: Figure 1-2. Ep9302 Block Diagram
JTAG AC’97 Memory Management Unit 3 USB 2.0 FS Host RTC with SW Trim Boot ROM High-Speed Bus (AHB) Watchdog Timer Vectored Inerrupts AHB/APB Bridge 4 Timers Peripheral Bus (APB) Figure 1-3. EP9307 Block Diagram DS785UM1 Copyright 2007 Cirrus Logic...
Page 32: Figure 1-4. Ep9312 Block Diagram
Memory Management Unit 3 USB 2.0 FS Host RTC with SW Trim 2 IDE High-Speed Bus (AHB) Watchdog Timer Boot ROM AHB/APB Bridge 4 Timers Vectored Peripheral Bus (APB) Inerrupts Figure 1-5. EP9315 Block Diagram DS785UM1 Copyright 2007 Cirrus Logic...
Page 33 - UART3 implements both a UART and an HDLC interface identical to that of UART1; • LCD and Analog Raster Interface in EP9307, 9312, and 9315 only • 2D Graphics Accelerator in EP9307and 9315 only - Line Draw DS785UM1 Copyright 2007 Cirrus Logic...
Page 34 • 30 in EP9307 only • 31 in EP9312 and 9315 only • Enhanced General-Purpose I/Os (EGPIOs) plus Port F GPIOs can generate interrupts: • 19 in EP9301, 9302 only • 18 in EP9307 only DS785UM1 Copyright 2007 Cirrus Logic...
Page 35: Ep93Xx Processor Applications
Co-processor for Ultra-Fast Math Processing The EP9302, EP9307, EP9312, and EP9315 processors include an advanced MaverickCrunch co-processor that provides mixed-mode math functions to greatly accelerate the floating-point processing capabilities of the ARM920T Core. The MaverickCrunch co- DS785UM1 Copyright 2007 Cirrus Logic...
Page 36: Maverickkey ™ Unique Id Secures Digital Content In Oem Designs
MaverickKey IDs can also be used by OEMs and design houses to protect against design piracy by presetting ranges for unique IDs. For more information on securing your design using MaverickKey, please contact your Cirrus Logic sales representative. 1.4.4 Integrated Multi-Port USB 2.0 Full Speed Hosts with Transceivers The EP9307, EP9312, and EP9315 processors integrate three USB 2.0 Full Speed Host...
Page 37: Integrated Ethernet Mac Reduces Bom Costs
1.4.5 Integrated Ethernet MAC Reduces BOM Costs The EP93xx processors integrate a 1/10/100 Mbps Ethernet Media Access Controller (MAC). With a simple connection to MII-based external PHYs (such as the Cirrus Logic CS8952 PHY Transceiver), an EP93xx processor-based system has easy, high-performance, cost-effective Internet capability.
Page 38: 12-Bit Analog-To-Digital Converter (Adc) Provides An Integrated Touch-Screen Interface Or General Adc Functionality
PCMCIA PC Cards. These PCMCIA cards are credit card sized peripherals that add memory, mass storage and I/O capabilities to computer systems, and can be used to further broaden the options of a designer’s platform. 1-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 39: Chapter 2. Arm920T Core And Advanced High-Speed Bus (Ahb)
• Translation Look-aside Buffers (TLB) with 64 Data and 64 Instruction Entries • Programmable Page Sizes of 64 kbyte, 4 kbyte, and 1 kbyte • Independent lockdown of TLB Entries • JTAG Interface for Debug Control • Co-processor Interface DS785UM1 Copyright 2007 Cirrus Logic...
Page 40: Block Diagram
1 Mbyte, 64 kbyte, 4 kbyte, 1 kbyte size blocks. To increase system performance, a 64-entry translation look-aside buffer will cache 64 address locations before a TLB miss occurs. DS785UM1 Copyright 2007 Cirrus Logic...
Page 41: Arm9Tdmi Core
There are six scan chains (0 through 5) in the ARM9TDMI controlled by the JTAG Test Access Port (TAP) controller. Details on the individual scan chain function and bit order can be found in the ARM920T Technical Reference Manual. DS785UM1 Copyright 2007 Cirrus Logic...
Page 42: Memory Management Unit
Access to specific instructions or data has three possible states: • Client: Access permissions based on the section or page table descriptor • Manager: Ignore access permissions in the section or page table descriptor • No access: any attempted access generates a domain fault DS785UM1 Copyright 2007 Cirrus Logic...
Page 43: Cache And Write Buffer
• If the I-Cache is disabled, current contents are ignored. If re-enabled before a reset, contents will be unchanged, but may not be coherent with eternal memory. If so, contents must be flushed before re-enabling. DS785UM1 Copyright 2007 Cirrus Logic...
Page 44: Co-Processor Interface
• Split Transactions • Bus Master hand-over to devices such as the MaverickCrunch co-processor or DMA controller • Single clock edge operations The APB (Advanced Peripheral Bus) is a lower bandwidth, but lower power, bus that provides: DS785UM1 Copyright 2007 Cirrus Logic...
Page 45: Ahb Implementation Details
This removes the need for three state buffers and bus holders, and simplifies bus arbitration. Figure 2-3 on page 2-8 shows the main data paths in the processor’s AHB implementation. DS785UM1 Copyright 2007 Cirrus Logic...
Page 46: Figure 2-3. Main Data Paths
Two different forms of burst transfers are allowed: • Incrementing bursts, which do not wrap at address boundaries • Wrapping bursts, which wrap at particular address boundaries. DS785UM1 Copyright 2007 Cirrus Logic...
Page 47: Memory And Bus Access Errors
The arbitration scheme can be broken down into three main areas: • The main AHB system bus Arbiter • The SDRAM slave interface Arbiter • The EBI bus Arbiter DS785UM1 Copyright 2007 Cirrus Logic...
Page 48: Main Ahb Bus Arbiter
Standby mode, the dummy master will be granted the bus, which simply performs IDLE transfers. In this way, all the masters except the ARM920T can be used during Halt mode, but are shutdown upon entry into Standby mode. 2-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 49: Sdram Slave Arbiter
An AHB Slave responds to transfers initiated by bus masters. The slave uses signals from the decoder to determine when it should respond to a bus transfer. All other signals required for the transfer, such as the address and control information, are generated by the bus master. DS785UM1 2-11 Copyright 2007 Cirrus Logic...
Page 50: Ahb-To-Apb Bridge
0x8087_0000 - 0x8087_FFFF Reserved 0x8086_0000 - 0x8086_FFFF Reserved 0x8085_0000 - 0x8085_FFFF Reserved 0x8084_0000 - 0x8084_FFFF GPIO 0x8083_0000 - 0x8083_FFFF Security 0x8082_0000 - 0x8082_FFFF 0x8081_0000 - 0x8081_FFFF Timers 0x8080_0000 - 0x8080_FFFF Reserved 0x8010_0000 - 0x807F_FFFF Reserved 2-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 51: Apb Slave
Banked register information is not shared between modes. FIQs bank the largest number of registers, and increase performance by reducing the need to push/pop registers from the stack. DS785UM1 2-13 Copyright 2007 Cirrus Logic...
Page 52: Table 2-5. Register Organization Summary
• r0-r12: General purpose read/write 32-bit registers • r13 (sp): Stack Pointer • r14 (lr): Link Register • r15 (pc): Program Counter • cpsr: Current Program Status Register containing condition codes and operating modes 2-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 53: Table 2-6. Cp15 Arm920T Register Description
Examples: MRC p15, 0, Rd, c10, c0, 1- Write lockdown base pointer for data TLB entry MRC p15, 0, Rd, c10, c0, 1 - Write lockdown base pointer for instruction TLB entry DS785UM1 2-15 Copyright 2007 Cirrus Logic...
Page 54: Memory Map
Async memory (nCS1) 0x0001_0000 - 0x0FFF_FFFF Sync memory (nSDCE3) Async memory (nCS0) Sync memory (nSDCE3) Async memory (nCS0) 0x0000_0000 - 0x0000_FFFF Internal Boot ROM Internal Boot ROM if INTBOOT is selected if INTBOOT is selected 2-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 55: Internal Register Map
M2P Channel 2 Registers (Tx) Memory-to-Peripheral Channel 2 Registers (Tx) 0x8000_00C0 - 0x8000_00FC M2P Channel 3 Registers (Rx) Memory-to-Peripheral Channel 3 Registers (Rx) 0x8000_0100 - 0x8000_013C M2M Channel 0 Registers Memory-to-Memory Channel 0 Registers DS785UM1 2-17 Copyright 2007 Cirrus Logic...
Page 56 MAC Receive Miss Count Register 0x8001_0078 RXRuntCnt MAC Receive Runt Count Register 0x8001_0080 BMCtl MAC Bus Master Control Register 0x8001_0084 BMSts MAC Bus Master Status Register 0x8001_0088 RXBCA MAC Receive Buffer Current Address Register 2-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 57 HcPeriodCurrentED USB Host Controller Period CurrentED 0x8002_0020 HcControlHeadED USB Host Controller Control HeadED 0x8002_0024 HcControlCurrentED USB Host Controller Control CurrentED 0x8002_0028 HcBulkHeadED USB Host Controller Bulk HeadED 0x8002_002C HcBulkCurrentED USB Host Controller Bulk CurrentED DS785UM1 2-19 Copyright 2007 Cirrus Logic...
Page 58 Word location of the top left corner of cursor to be displayed 0x8003_0064 CursorAdrReset Location of first word of cursor to be scanned after last line 0x8003_0068 CursorSize Cursor height, width, and step size Register 2-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 59 SMC and PCMCIA Control Registers 0x8008_xxxx Bank config Register 0 (used to program characteristics of the 0x8008_0000 SMCBCR0 SRAM/ROM memory) Bank config Register 1 (used to program characteristics of the 0x8008_0004 SMCBCR1 SRAM/ROM memory) DS785UM1 2-21 Copyright 2007 Cirrus Logic...
Page 60 IDE UDMA Debug Register 0x800A_0030 IDEUDMAWrBufSts IDE UDMA Write Buffer Status Register 0x800A_0034 IDEUDMARdBufSts IDE UDMA Read Buffer Status Register VIC1 Vectored Interrupt Controller 1 Registers 0x800B_xxxx 0x800B_0000 VIC1IRQStatus IRQ status Register 0x800B_0004 VIC1FIQStatus FIQ status Register 2-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 61 Vector control 12 Register 0x800B_0234 VIC1VectCntl13 Vector control 13 Register 0x800B_0238 VIC1VectCntl14 Vector control 14 Register 0x800B_023C VIC1VectCntl15 Vector control 15 Register 0x800B_0FE0 VIC1PeriphID0 VIC Identification Register bits 7:0 0x800B_0FE4 VIC1PeriphID1 VIC Identification Register bits 15:8 DS785UM1 2-23 Copyright 2007 Cirrus Logic...
Page 62 Vector control 5 Register 0x800C_0218 VIC2VectCntl6 Vector control 6 Register 0x800C_021C VIC2VectCntl7 Vector control 7 Register 0x800C_0220 VIC2VectCntl8 Vector control 8 Register 0x800C_0224 VIC2VectCntl9 Vector control 9 Register 0x800C_0228 VIC2VectCntl10 Vector control 10 Register 2-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 63 I2STX2Rt Right Transmit data Register for channel 2 0x8082_0028 I2STXLinCtrlData Transmit Line Control Register 0x8082_002C I2STXCtrl Transmit Control Register 0x8082_0030 I2STXWrdLen Transmit Word Length 0x8082_0034 I2STX0En TX0 Channel Enable 0x8082_0038 I2STX1En TX1 Channel Enable DS785UM1 2-25 Copyright 2007 Cirrus Logic...
Page 64 RX2 Channel Enable SECURITY Security Registers 0x8083_xxxx 0x8083_2714 ExtensionID Contains the Part ID for EP93XX devices Contact Cirrus Logic for details regarding implementation of device Security measures. GPIO GPIO Control Registers 0x8084_xxxx 0x8084_0000 PADR GPIO Port A Data Register 0x8084_0004...
Page 65 Interrupt Enable 0x8088_001C Reserved 0x8088_0020 AC97DR2 Data read or written from/to FIFO2 0x8088_0024 AC97RXCR2 Control Register for receive 0x8088_0028 AC97TXCR2 Control Register for transmit 0x8088_002C AC97SR2 Status Register 0x8088_0030 AC97RISR2 Raw interrupt status Register DS785UM1 2-27 Copyright 2007 Cirrus Logic...
Page 66 SPI1 Data Register 0x808A_000C SSP1SR SPI1 Status Register 0x808A_0010 SSP1CPSR SPI1 Clock Prescale Register 0x808A_0014 SSP1IIR SPI1 Interrupt/Interrupt Clear Register IrDA IrDA Control Registers 0x808B_xxxx 0x808B_0000 IrEnable IrDA Interface Enable 0x808B_0004 IrCtrl IrDA Control Register 2-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 67 UART2 Line Control Register - Low Byte 0x808D_0014 UART2Ctrl UART2 Control Register 0x808D_0018 UART2Flag UART2 Flag Register 0x808D_001C UART2IntIDIntClr UART2 Interrupt ID and Interrupt Clear Register 0x808D_0020 UART2IrLowPwrCntr UART2 IrDA Low-power Counter Register 0x808D_0028 UART2DMACtrl UART2 DMA Control Register DS785UM1 2-29 Copyright 2007 Cirrus Logic...
Page 68 Touchscreen Direct Control Touch Detect Register 0x8090_0020 TSSWLock Touchscreen Software Lock Register 0x8090_0024 TSSetup2 Touchscreen Setup Register 2 PWM Control Registers 0x8091_xxxx 0x8091_0000 PWM0TermCnt PWM0 Terminal Count 0x8091_0004 PWM0DutyCycle PWM0 Duty Cycle 0x8091_0008 PWM0En PWM0 Enable 2-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 69 KeyTchClkDiv Keyscan/Touch Clock Divider 0x8093_0094 ChipID Chip ID Register 0x8093_009C SysCfg System Configuration 0x8093_00C0 SysSWLock Syscon Software Lock Register 0x8094_xxxx WATCHDOG Watchdog Control Register 0x8094_0000 Watchdog Watchdog Timer Register 0x8094_0004 WDStatus Watchdog Status Register DS785UM1 2-31 Copyright 2007 Cirrus Logic...
Page 70 ARM920T Core and Advanced High-Speed Bus (AHB) EP93xx User’s Guide Table 2-8. Internal Register Map (Continued) Address Register Name Register Description Lock 0x8095_0000 - 0x8FFF_FFFF Reserved 2-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 71: Chapter 3. Maverickcrunch Co-Processor
ARM920T via the co-processor bus and shares the instruction stream and memory interface of the ARM920T. It runs at the ARM920T core clock frequency (either FCLK or BCLK). The co-processor supports four primary data formats: DS785UM1 Copyright 2007 Cirrus Logic...
Page 72 IEEE-754 rounding and exceptions are also provided. Four rounding modes for floating point operations are: • round to nearest ∞ • round toward ∞ • round toward • round toward 0 Exceptions include: • Invalid operator • Overflow • Underflow DS785UM1 Copyright 2007 Cirrus Logic...
Page 73: Pipelines And Latency
A single precision floating point value is stored in the upper 32 bits of a 64-bit register and must be explicitly promoted to double precision to be used in double precision calculations: Opcode 32 31 Sign Exponent Significand not used DS785UM1 Copyright 2007 Cirrus Logic...
Page 74: Integer Saturation Arithmetic
Setting the UI bit causes the MaverickCrunch co-processor to treat all 32-bit and 64-bit integer operations as unsigned with respect to overflow, underflow, saturation, and comparison. DS785UM1 Copyright 2007 Cirrus Logic...
Page 75: Table 3-1. Saturation For Non-Accumulator Instructions
The bit format x.yy represents x binary bits before the decimal point and yy fraction bits after the decimal point, as for example, when the bit format 2.62 has two binary bits and sixty-two fraction bits. Though these formats utilize either 32- or 64-bit integers, the accumulators are DS785UM1 Copyright 2007 Cirrus Logic...
Page 76: Comparisons
All compare operations update both the FCC[1:0] bits in the DSPSC register and an ARM register. Though any of the ARM general purpose registers r0 through r14 may be specified as the destination, specifying r15 actually updates the CPSR flag bits NZCV. This permits the DS785UM1 Copyright 2007 Cirrus Logic...
Page 77: Table 3-3. Comparison Relationships And Their Results
Signed Greater Than or Equal Greater Than or Equal < 1011 Signed Less Than Less Than > 1100 Signed Greater Than Greater Than ≤ 1101 Signed Less Than or Equal Less Than or Equal 1110 Always (unconditional) Always (unconditional) 1111 Never Never DS785UM1 Copyright 2007 Cirrus Logic...
Page 78: Programming Examples
; data section preloaded with 0x0 (“num”) cfldr32 c1, [r0, #0x4] ; data section preloaded with 0xa cfldr32 c2, [r0, #0x8] ; data section preloaded with 0x1 cfldr32 c3, [r0, #0xc] ; data section preloaded with 0x5 DS785UM1 Copyright 2007 Cirrus Logic...
Page 79: Example 2
; m *= 4 outer_loop r12, r3 ; j = m * 4 cfsub64 c0, c0, c0 ; int_sum = 0; cfcvt32s c0, c0 ; sum = float(int_sum); inner_loop cfldrs c2, [r0], #4 ; c2 = *data++; DS785UM1 Copyright 2007 Cirrus Logic...
Page 80: Dspsc Register
Reserved. Unknown During Read. INST: Exception Instruction. Whenever an unmasked exception occurs, these 32 bits are loaded with the instruction that caused the exception. Hence, this contains the instruction that caused the most recent unmasked exception. 3-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 81 . E x c e p t i o n s m a y b e individually enabled by other bits in this register (IXE, UFE, OFE, and IOE). This bit has no effect if no exceptions are enabled: 0 = Exceptions are synchronous 1 = Exceptions are asynchronous DS785UM1 3-11 Copyright 2007 Cirrus Logic...
Page 82 ∞ 1 1 = Round to IXE: Inexact Trap Enable. Enables/disables software trapping for IEEE 754 inexact exceptions: 0 = Disable software trapping for inexact exceptions 1 = Enable software trapping for inexact exceptions 3-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 83 Writing a “0” to this position clears the status bit. 0 = No invalid operator exception detected 1 = Invalid operator exception detected DS785UM1 3-13 Copyright 2007 Cirrus Logic...
Page 84: Arm Co-Processor Instruction Format
12 11 cond 1110 opcode1 cp num opcode2 MRC (Move to ARM Register from Co-Processor) Instruction Format 28 27 24 23 21 20 19 16 15 12 11 cond 1110 opcode1 cp num opcode2 3-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 85: Table 3-5. Condition Code Definitions
• U: Specifies whether the supplied 8-bit offset is added to a base register (U=1) or subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch co- processor. • N: Specifies the width of a data type involved in a move operation. The MaverickCrunch DS785UM1 3-15 Copyright 2007 Cirrus Logic...
Page 86: Table 3-6. Ldc/Stc Opcode Map
0110 cfmsub32 0100 cfmval32 cfmvam32 cfmvah32 cfmva32 cfmva64 cfmvsc32 0101 cfsh64 0110 cfmadda32 0100 cfabss cfabsd cfnegs cfnegd cfadds cfaddd cfsubs cfsubd 0101 cfabs32 cfabs64 cfneg32 cfneg64 cfadd32 cfadd64 cfsub32 cfsub64 0110 cfmsuba32 3-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 87: Instruction Set For The Maverickcrunch Co-Processor
'1' or '0'. Any field whose value may vary, such as a register index, is named as in the ARM programming manuals, and its function described below. DS785UM1 3-17 Copyright 2007 Cirrus Logic...
Page 88: Table 3-10. Maverickcrunch Instruction Set
Move 32-bit integer from CRn[31:0] to accumulator CRd[31:0] and sign cfmva32 CRd, CRn extend through bit 71 Move 64-bit integer from CRn to accumulator CRd[63:0] and sign extend cfmva64 CRd, CRn through bit 71 3-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 89 Shift 32-bit integer in CRn by <imm> bits and store in CRd, where <imm> <imm> is between -32 and 31, inclusive cfsh64 CRd, CRn, Shift 64-bit integer in CRn by <imm> bits and store in CRd, where <imm> <imm> is between -32 and 31, inclusive DS785UM1 3-19 Copyright 2007 Cirrus Logic...
Page 90 CRd gets the product of CRn and CRm cfmac32 CRd, CRn, CRd gets sum of CRd and the product of CRn and CRm cfmsc32 CRD, CRn, CRd gets CRd minus the product of CRn and CRm 3-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 91: Load And Store Instructions
Table 3-11. Mnemonic Codes for Loading Floating Point Value from Memory Mnemonic Addressing Mode CFLDRS<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed CFLDRS<cond> CRd, [Rn], <offset> Immediate post-indexed CFLDRD<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed CFLDRD<cond> CRd, [Rn], <offset> Immediate post-indexed DS785UM1 3-21 Copyright 2007 Cirrus Logic...
Page 92: Table 3-12. Mnemonic Codes For Loading Integer Value From Memory
Store Floating Point Values to Memory 31:28 27:25 19:16 15:12 11:8 cond 1 1 0 0 1 0 0 8_bit_word_offset Description: Stores a single or double precision floating point value from a MaverickCrunch register into memory. 3-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 93: Table 3-13. Mnemonic Codes For Storing Floating Point Values To Memory
Immediate post-indexed CFSTR64<cond> CRd, [Rn, <offset>]{!} Immediate pre-indexed CFSTR64<cond> CRd, [Rn], <offset> Immediate post-indexed Bit Definitions: Integer width - 0 for 32-bit integer, 1 for 64-bit integer Base register in ARM CRd: Source register. DS785UM1 3-23 Copyright 2007 Cirrus Logic...
Page 94: Move Instructions
Moves the lower half of a double precision floating point value from an ARM register into the lower half of a MaverickCrunch register. Mnemonic: CFMVDLR<cond> CRn, Rd Bit Definitions: CRn: Destination register Source ARM register 3-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 95 0 0 1 Description: Moves the upper half of a double precision floating point value stored in a MaverickCrunch register into an ARM register. Mnemonic: CFMVRDH<cond> Rd, CRn Bit Definitions: Destination ARM register CRn: Source register DS785UM1 3-25 Copyright 2007 Cirrus Logic...
Page 96 0 0 1 Description: Moves the upper half of a 64-bit integer from an ARM register into the upper half of a MaverickCrunch register. Mnemonic: CFMV64HR<cond> CRn, Rd Bit Definitions: CRn: Destination register Source ARM register 3-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 97: Accumulator And Dspsc Move Instructions
0 1 0 Description: Moves the lowest 32 bits of an accumulator (31:0) to the low 32 bits of a MaverickCrunch register. Mnemonic: CFMV32AL<cond> CRd, CRn Bit Definitions: CRd: Destination register CRn: Source accumulator DS785UM1 3-27 Copyright 2007 Cirrus Logic...
Page 98 1 0 0 Description: Moves the lowest 8 bits (7:0) of a MaverickCrunch register to the highest 8 bits of an accumulator (71:64). Mnemonic: CFMVAH32<cond> CRd, CRn Bit Definitions: CRd: Destination accumulator CRn: Source register 3-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 99 0 1 0 0 1 0 1 Description: Moves a 32-bit value from a MaverickCrunch register to an accumulator and sign extend to 72 bits. Mnemonic: CFMVA32<cond> CRd, CRn Bit Definitions: CRd: Destination accumulator CRn: Source register DS785UM1 3-29 Copyright 2007 Cirrus Logic...
Page 100 1 1 1 Description: Moves a 64-bit value from a MaverickCrunch register to the MaverickCrunch Status/Control register, DSPSC. All DSPSC bits are writable. CRn is ignored. Mnemonic: CFMVSC32<cond> CRd, CRn Bit Definitions: CRd: Source register 3-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 101: Copy And Conversion Instructions
1 1 1 0 0 1 0 0 0 0 1 Description: Copies a double precision floating point value from one register to another. Mnemonic: CFCPYD<cond> CRd, CRn Bit Definitions: CRd: Destination register CRn: Source register DS785UM1 3-31 Copyright 2007 Cirrus Logic...
Page 102 1 1 1 0 0 1 0 0 1 0 0 Description: Converts a 32-bit integer to a single precision floating point value. Mnemonic: CFCVT32S<cond> CRd, CRn Bit Definitions: CRd: Destination register CRn: Source register 3-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 103 1 1 1 0 0 1 0 0 1 1 1 Description: Converts a 64-bit integer to a double precision floating point value. Mnemonic: CFCVT64D<cond> CRd, CRn Bit Definitions: CRd: Destination register CRn: Source register DS785UM1 3-33 Copyright 2007 Cirrus Logic...
Page 104 27:24 23:22 21:20 19:16 15:12 11:8 cond 1 1 1 0 0 1 0 1 1 1 1 Description: Truncates a double precision floating point number to a 32-bit integer. Mnemonic: CFTRUNCD32<cond> CRd, CRn 3-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 105: Shift Instructions
This instruction may also be used to copy a 64-bit integer from one register to another using a shift value of 0. Mnemonic: CFRSHL64<cond> CRm, CRn, Rd Bit Definitions: CRm: Destination register CRn: Source register Shift count register in ARM DS785UM1 3-35 Copyright 2007 Cirrus Logic...
Page 106: Compare Instructions
N, Z, C, and V bits, respectively, in the ARM920T’s program status register, while the bottom 28 bits are zeros. If Rd = 15, then the four status bits are stored in the ARM status register, CPSR. 3-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 107 28 bits are zeros. If Rd = 15, then the four status bits are stored in the ARM status register, CPSR. Mnemonic: CFCMP32<cond> Rd, CRn, CRm Bit Definitions: CRn: First source register CRm: Second source register DS785UM1 3-37 Copyright 2007 Cirrus Logic...
Page 108: Floating Point Arithmetic Instructions
27:24 23:22 21:20 19:16 15:12 11:8 cond 1 1 1 0 0 1 0 0 0 0 1 Description: Computes the absolute value of a double precision floating point number. Mnemonic: CFABSD<cond> CRd, CRn 3-38 DS785UM1 Copyright 2007 Cirrus Logic...
Page 109 0 1 0 0 1 0 0 Description: Adds two single precision floating point numbers: CRd = CRn + CRm Mnemonic: CFADDS<cond> CRd, CRn, CRm Bit Definitions: CRd: Destination register CRn: Addend register CRm: Addend register DS785UM1 3-39 Copyright 2007 Cirrus Logic...
Page 110 1 1 1 0 0 1 0 0 1 1 1 Description: Subtracts two double precision floating point numbers. Mnemonic: CFSUBD<cond> CRd, CRn, CRm Bit Definitions: CRd: Destination register CRn: Minuend register CRm: Subtrahend register 3-40 DS785UM1 Copyright 2007 Cirrus Logic...
Page 111: Integer Arithmetic Instructions
11:8 cond 1 1 1 0 0 1 0 1 0 0 0 Description: Computes the absolute value of a 32-bit integer. Mnemonic: CFABS32<cond> CRd, CRn Bit Definitions: CRd: Destination register CRn: Source register DS785UM1 3-41 Copyright 2007 Cirrus Logic...
Page 112 Bit Definitions: CRd: Destination register CRn: Source register 32-bit Integer Add 31:28 27:24 23:22 21:20 19:16 15:12 11:8 cond 1 1 1 0 0 1 0 1 1 0 0 Description: Adds two 32-bit integers. 3-42 DS785UM1 Copyright 2007 Cirrus Logic...
Page 113 Subtrahend register 64-bit Integer Subtract 31:28 27:24 23:22 21:20 19:16 15:12 11:8 cond 1 1 1 0 0 1 0 1 1 1 1 Description: Subtracts two 64-bit integers. Mnemonic: CFSUB64<cond> CRd, CRn, CRm DS785UM1 3-43 Copyright 2007 Cirrus Logic...
Page 114 1 1 1 0 0 1 0 1 0 1 0 Description: Multiplies two 32-bit integers and adds the result to another 32-bit integer: × CRd = CRd + (CRn CRm) Mnemonic: CFMAC32<cond> CRd, CRn, CRm 3-44 DS785UM1 Copyright 2007 Cirrus Logic...
Page 115: Accumulator Arithmetic Instructions
Multiplies two 32-bit integers, adds the product to a third 32-bit integer, and stores the result in an accumulator: × CRa = CRd + (CRn CRm) Mnemonic: CFMADD32<cond> CRa, CRd, CRn, CRm Bit Definitions: CRa: Destination accumulator CRd: Addend register CRn: Multiplicand register CRm: Multiplicand register DS785UM1 3-45 Copyright 2007 Cirrus Logic...
Page 116 Multiplies two 32-bit integers, adds the product to an accumulator, and stores the result in an accumulator: × CRa = CRd + (CRn CRm) Mnemonic: CFMADDA32<cond> CRa, CRd, CRn, CRm Bit Definitions: CRa: Destination accumulator CRd: Addend accumulator CRn: Multiplicand register CRm: Multiplicand register 3-46 DS785UM1 Copyright 2007 Cirrus Logic...
Page 117 × CRa = CRd - (CRn CRm) Mnemonic: CFMSUBA32<cond> CRa, CRd, CRn, CRm Bit Definitions: CRa: Destination accumulator CRd: Specifies minuend accumulator CRn: Multiplicand register CRm: Multiplicand register DS785UM1 3-47 Copyright 2007 Cirrus Logic...
Page 118 MaverickCrunch Co-Processor EP93xx User’s Guide 3-48 DS785UM1 Copyright 2007 Cirrus Logic...
Page 119: Chapter 4. Boot Rom
• UART1: Code is downloaded through UART1 into an on chip buffer and executed • SPI Serial Flash: Code is copied from an SPI Serial Flash into an on-chip buffer and executed • FLASH: Code present in external FLASH memory is executed directly DS785UM1 Copyright 2007 Cirrus Logic...
Page 120: Image Header
C. Read 2048 (decimal count) characters from UART1 and store these in the internal Boot buffer (alias for the Ethernet Mac buffer) D. Output a “>” to signify 2048 characters have been read E. Turn on Green LED F. Jump to the start of the internal Boot Buffer DS785UM1 Copyright 2007 Cirrus Logic...
Page 121: Flowchart
13.If “CRUS” or “SURC” HeaderID is not found, copy dummy vectors into low SDRAM, and then follow Step A. A. Flash Green LED 4.1.2.3 Flowchart Figure 4-1 provides a flow chart for operation of the Boot ROM software. DS785UM1 Copyright 2007 Cirrus Logic...
Page 122: Boot Options
Sync Boot ? SDCS (0 or 3) See 4.2.4 Copy Vectors Flash Green Led Figure 4-1. Flow Chart of Boot ROM Software 4.2 Boot Options Table 4-1 shows configuration settings that are common to all boot modes. DS785UM1 Copyright 2007 Cirrus Logic...
Page 123: Table 4-1. Boot Configuration Options
CSn[7:6] value: 8-bit 16-bit 32-bit 32-bit See memory map in Table 2-7 on page 2-16 ASYNC boot mode. Note: ASYNC boot mode is the preferred boot mode type for new designs. DS785UM1 Copyright 2007 Cirrus Logic...
Page 124: Uart Boot
Code execution will start at address FLASH base + 0x4. The ARM Core will be in SVC mode. Alternatively, to boot from FLASH, put the ASCII “CRUS” or “SURC” value in the HeaderID at one of the following locations (this location will be referred to as FLASH base +0x1000): 0x1000_1000 0x2000_1000 DS785UM1 Copyright 2007 Cirrus Logic...
Page 125: Sdram Or Syncflash Boot
Code execution will start at address Base + 0x0. The ARM Core will be in SVC mode. 4.2.5 Synchronous Memory Operation If running from Synchronous memory, before issuing a software reset, perform this procedure: 1. Run from SDRAM 2. Perform a software reset (SWRST bit in DEVCFG register) DS785UM1 Copyright 2007 Cirrus Logic...
Page 126 3. Run the internal boot code and boot from FLASH 4. Set the PLL back to use the external clock 5. Set up the SDRAM 6. Load the programs to SDRAM 7. Run from SDRAM DS785UM1 Copyright 2007 Cirrus Logic...
Page 127: Chapter 5. System Controller
The device system reset consists of several events and signals. It has four levels of reset control: • Power-on-reset, controlled by PRSTn pin. It resets the entire processor with no exceptions. • User reset, controlled by RSTOn pin. While active, it resets the entire processor, except DS785UM1 Copyright 2007 Cirrus Logic...
Page 128: Hardware Configuration Control
Note that the signals EECLK and EEDAT may have 1 kΩ pull-up resisters if used in an open-drain two-wire serial port application. (The default state assignments will assume these pull-ups.) The Hardware Control configurations are show in Table 5-2. DS785UM1 Copyright 2007 Cirrus Logic...
Page 129: Table 5-2. Boot Configuration Options
Internal boot using Async boot mode at the chip select where the HeaderID exists. The selection of the bus width is determined by latched CSn[7:6] value: 8-bit 16-bit 32-bit 32-bit See memory map in Table 2-7 on page 2-16 ASYNC boot mode. DS785UM1 Copyright 2007 Cirrus Logic...
Page 130: Software System Configuration Options
“PLL1” is used in the figure, it applies to PLL2 as well. 14.7456 Input Divider PLL1_X1 PLL1_X2 Fout PLL1_X2IPD 2^(PLL1_PS) Feedback Divider Feedback Divider PLL1_X1FBD PLL1_X2FBD Figure 5-1. Phase Locked Loop (PLL) Structure DS785UM1 Copyright 2007 Cirrus Logic...
Page 131: Bus And Peripheral Clock Generation
• PLL1_X2 output, BEFORE the PS divide, must be > 290 MHz and <= 528 MHz The same conditions apply to PLL2 and the "ClkSet2" register. 5.1.5.2 Bus and Peripheral Clock Generation Figure 5-2 illustrates the clock generation system. DS785UM1 Copyright 2007 Cirrus Logic...
Page 132: Figure 5-2. Clock Generation System
TOUCH_CLK Touch ADC_CLK Clock FILT_CLK Figure 5-2. Clock Generation System 5.1.5.2.1 Bus Clock Generation Figure 5-3 shows the generated clocks: the CPU clock (FCLK), the AHB bus clock (HCLK), and the APB bus clock (PCLK). DS785UM1 Copyright 2007 Cirrus Logic...
Page 133: Figure 5-3. Bus Clock Generation
There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and PCLK<=50 MHz and FCLK >= HCLK > PCLK. Refer to register, “ClkSet1” on page 5-18, for the detailed configuration information regarding the divider bit fields. DS785UM1 Copyright 2007 Cirrus Logic...
Page 134: Table 5-3. Clock Speeds And Sources
From the 14.7456MHz external oscillator 2.9491 MHz Divided-by-5 from the 14.7456MHz external oscillator 508.4689 KHz Timers 1.9939 KHz All divided by the 14.7456 MHz external oscillator 983 KHz Watchdog 256 Hz Tap from the 32 KHz RTC clock DS785UM1 Copyright 2007 Cirrus Logic...
Page 135: Steps For Clock Configuration
5.1.6.1 Clock Gatings The list of peripherals with PCLK gating is shown Table 5-4. Refer to the appropriate chapter in this user’s guide to find detailed information about clock gatings for a specific peripheral. DS785UM1 Copyright 2007 Cirrus Logic...
Page 136: System Power States
• Run mode: Normal operation mode. • Halt: ARM Core stops executing instructions. • Standby: Power is on, but only SDRAM self-refresh and the RTC run. Figure 5-4 illustrates the transitions among power states. 5-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 137: Figure 5-4. Power States And Transitions
When the EP93xx normally enters Standby mode, the SDRAM controller puts the external SDRAM into self-refresh before disabling its clocks (see “SDRAM Self Refresh” on page 13- 8). This condition is only true if the refresh enable bit (RFSHEN) in the SDRAM controller is DS785UM1 5-11 Copyright 2007 Cirrus Logic...
Page 138: Interrupt Generation
TICK interrupt is still active. In other words, if a TICK interrupt has not been served for a complete TICK period, a watchdog expired interrupt is generated. It can be cleared by writing to the TEOI location as well. 5-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 139: Registers
MIR Clock Divider, divides MIR clock for 0x8093_0088 MIRClkDiv MIR IrDA 0x8093_008C I2SClkDiv S Audio Clock Divider 0x8093_0090 KeyTchClkDiv Keyscan/Touch Clock Divider 0x8093_0094 ChipID Chip ID Register 0x8093_009C SysCfg System Configuration 0x8093_00A0 Reserved 0x8093_00C0 SysSWLock 1 bit Software Lock Register DS785UM1 5-13 Copyright 2007 Cirrus Logic...
Page 140 Standby state, or PLL2 is powered down. SW_RESET: Software reset flag. This bit is set if the software reset has been activated. It is cleared by writing to the STFClr location. On power-on-reset, it is reset to 0b. 5-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 141 For the device, this value is 0x43. PwrCnt FIR_EN RSVD UART USH_EN BAUD RSVD Address: 0x8093_0004 - Read / Write Definition: The PwrCnt system control register is the Clock/Debug control status register. Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 5-15 Copyright 2007 Cirrus Logic...
Page 142 This bit is used to gate the FIRCLK to the IrDA block in order to save power. It is reset to zero, thus gating off the FIRCLK. Setting this bit to one will turn on the 48 MHz clock to the IrDA. 5-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 143 Writing to the TEOI location will clear the periodic Watchdog expired interrupt (WEINT) and the 64 Hz TICK interrupt (TINT). Any data written to the register triggers the clearing. Bit Descriptions: RSVD: There are no readable bits in this register. DS785UM1 5-17 Copyright 2007 Cirrus Logic...
Page 144 PLL1_X2IPD: These 5 register bits set the input divider for PLL1 operation. On power-on-reset the value is set to 00111b (7 decimal). Note: The value in the register is the actual coefficient minus one. 5-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 145 001 - Divide by 2 101 - Divide by 8 010 - Divide by 4 110 - Divide by 16 011 - Divide by 5 111 - Divide by 32 On power-on-reset the value is set to 000b. DS785UM1 5-19 Copyright 2007 Cirrus Logic...
Page 146 PLL2_X2IPD: These 5 register bits set the input divider for PLL2 operation. On power-on-reset the value is set to 10111b (23 decimal). Note: The value in the register is the actual coefficient minus one. 5-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 147 0101 - Divide by 6 1101 - Divide by 14 0110 - Divide by 7 1110 - Divide by 15 0111 - Divide by 8 1111 - Divide by 1 On power-on-reset these bits are reset to 0000b. DS785UM1 5-21 Copyright 2007 Cirrus Logic...
Page 148 NO_WRITE_WAIT:Used in the AHB/APB bridge to not insert an AHB wait during writes, if set. If reset, a wait state is added by forcing HREADY = 0 during ST_WRITE. This bit resets to 0x0001. 5-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 149: Table 5-6. Priority Order For Ahb Arbiter
When set the arbiter will degrant DMA from the AHB bus and will ignore subsequent requests from DMA if an IRQ is active. When IRQ is cleared the DMA request is allowed again. There is no impact on other masters. Reset to 0. DS785UM1 5-23 Copyright 2007 Cirrus Logic...
Page 150 ROM remap function causing the internal boot ROM to map to address zero, if internal boot is selected. Writing BootModeClr removes the internal ROM address remap, restoring normal address space. Bit Descriptions: RSVD: There are no readable bits in this register. 5-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 151 Raster On SDRAM Port 3. 1 - The Raster video refresh SDRAM accesses use the system primary AHB to get video data. 0 - Raster video refresh uses the private AHB on SDRAM Port 0. DS785UM1 5-25 Copyright 2007 Cirrus Logic...
Page 152: Table 5-7. Audio Interfaces Pin Assignment
PWM 1 output on EGPIO pin GonIDE: GPIO Port G on IDE pins 0 - GPIO Port G used for IDE 1 - GPIO Port G used for GPIO HonIDE: GPIO Port H on IDE pins 5-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 153 0 - Raster engine uses internal pixel clock and the SPCLK pin is configured as an output. U2EN: UART2 Enable. 1 - UART2 baud rate clock is active. 0 - UART2 clock is off. DS785UM1 5-27 Copyright 2007 Cirrus Logic...
Page 154 External DMA0 hardware handshake signals mapped to EGPIO pins. 1 - Signals mapped. 0 - Signals not supported. D1onG: External DMA1 hardware handshake signals mapped to EGPIO pins. 1 - Signals mapped. 0 - Signals not supported. 5-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 155 10 - Divide-by-2.5 11 - Divide-by-3 VDIV: VCLK divider value. Forms a divide-by-N of the pre-divide clock output. VCLK is the source clock divided by PDIV divided by N. Must be at least two. DS785UM1 5-29 Copyright 2007 Cirrus Logic...
Page 156 00 - Disable clock 01 - Divide-by-2 10 - Divide-by-2.5 11 - Divide-by-3 MDIV: MIR_CLK divider value. Forms a divide-by-N of the pre- divide clock output. MIR_CLK is the source clock divided by PDIV divided by N. 5-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 157 0 - LRCLK transitions on the rising SCLK edge. LRDIV: LRCLK divide select. 00 - LRCK = SCLK / 32 01 - LRCK = SCLK / 64 10 - LRCK = SCLK / 128 11 - Reserved DS785UM1 5-31 Copyright 2007 Cirrus Logic...
Page 158 Configures the Key Matrix, Touchscreen, and ADC clocks. Touchscreen clock is a fixed divide-by-4 from the ADC clock. Touch Filter clock is a fixed divide- by-2 from the ADC clock. Bit Descriptions: RSVD: Reserved. Unknown During Read. TSEN: Touchscreen and ADC clock enable 5-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 159 REV: Revision: Reads chip Version number: 0011 - Rev D0 0100 - Rev D1 0101 - Rev E0 0110 - Rev E1 0111 - Rev E2 Reads zero. ID[15:0]: Chip ID Number, reads 9213. DS785UM1 5-33 Copyright 2007 Cirrus Logic...
Page 160 LASDO: Latched version of ASDO pin. Used to select synchronous versus asynchronous boot device. LEEDA: Latched version of EEDAT pin. LEECLK: Define Internal or external boot: 1 - Internal 0 - External 5-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 161 Reserved. Unknown During Read. LOCK: Lock code value. This field must be written to a value of 0xAA to open the software lock. Reads 0x01 when the lock is open, 0x00 when the lock is closed. DS785UM1 5-35 Copyright 2007 Cirrus Logic...
Page 162 System Controller EP93xx User’s Guide 5-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 163 2 HCLK cycles. To work around this problem, first check for pending non-vectored VIC1 interrupts in the interrupt routine. If there are none then return from interrupt. The interrupt will immediately re-occur with the correct vector address. DS785UM1 Copyright 2007 Cirrus Logic...
Page 164: Chapter 6. Vectored Interrupt Controller
0 to vectored interrupt 15. Non-vectored IRQ interrupts have the lowest priority. Any of the non-vectored Interrupts can be either FIQ or IRQ (the interrupt type is determined by programming the appropriate register, ‘VICxIntSelect’ on page 6-11). DS785UM1 Copyright 2007 Cirrus Logic...
Page 165: Interrupt Configuration
UART1TXINTR1 UART 1 Transmit Interrupt UART2RXINTR2 UART 2 Receive Interrupt UART2TXINTR2 UART 2 Transmit Interrupt UART3RXINTR3 UART 3 Receive Interrupt UART3TXINTR3 UART 3 Transmit Interrupt INT_KEY Keyboard Matrix Interrupt INT_TOUCH Touch Screen Controller Interrupt Reserved DS785UM1 Copyright 2007 Cirrus Logic...
Page 166: Interrupt Details
ARM Core. Refer to the ARM Technical Reference Manual. COMMTX ARM Communication Channel Transmit. When high COMMTX indicates that the communications channel transmit buffer is empty. Refer to the ARM Technical Reference Manual. DS785UM1 Copyright 2007 Cirrus Logic...
Page 167 Memory-to-Memory (incorporating external M2P/P2M) Channel 0 Interrupt. See Chapter "DMA Controller". DMAM2M1 Memory-to-Memory (incorporating external M2P/P2M) Channel 1 Interrupt. See Chapter "DMA Controller". UART1RXINTR1 UART 1 Receive Interrupt. See Chapter 14, "UART1 With HDLC and Modem Control Signals" DS785UM1 Copyright 2007 Cirrus Logic...
Page 168 Clock With Software Trim". INT_IrDA IrDA Interrupt. See Chapter 17, "IrDA". INT_MAC Ethernet MAC Interrupt. See Chapter "1/10/100 Mbps Ethernet LAN Controller". INT_PROG Programmable Interrupt. See Chapter "Raster Engine With Analog/LCD Integrated Timing and Interface". DS785UM1 Copyright 2007 Cirrus Logic...
Page 169: Chapter 7. Raster Engine With Analog/Lcd Integrated
All these sources are individually maskable within UART3. See Chapter "UART3 With HDLC Encoder". USHINTR USB Host Interrupt. See Chapter 11, “USB Host Controller”. INT_PME PME interrupt. See Chapter 23 "Synchronous Serial Port". DS785UM1 Copyright 2007 Cirrus Logic...
Page 170: Table 6-2. Vicx Register Summary
VIC base + 013C Read /Write 0x0000_0000 VICxVectAddr15 Vector address 15 register VIC base + 0200 Read /Write 0x00 VICxVectCntl0, Vector control 0 register VIC base + 0204 Read /Write 0x00 VICxVectCntl1, Vector control 1 register DS785UM1 Copyright 2007 Cirrus Logic...
Page 171 Vectored Interrupt Controller (VIC). The read-only Reset Values are hard- wired. Consequently, the VICxPeriphID[3:0] registers are not included in the following Register Descriptions. Register Descriptions VICxIRQStatus IRQStatus IRQStatus Address: VIC1IRQStatus: 0x800B_0000 - Read Only VIC2IRQStatus: 0x800C_0000 - Read Only DS785UM1 Copyright 2007 Cirrus Logic...
Page 172 VICxIntEnable and VICxIntSelect registers. A “1” indicates that the interrupt is active, and generates an interrupt to the ARM Core. VICxRawIntr RawIntr RawIntr Address: VIC1RawIntr: 0x800B_0008 - Read Only VIC2RawIntr: 0x800C_0008 - Read Only 6-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 173 FIQ or an IRQ interrupt. Bit Descriptions: IntSelect: Selects type of interrupt for interrupt request: 1 = FIQ interrupt 0 = IRQ interrupt. VICxIntEnable IntEnable IntEnable Address: VIC1IntEnable: 0x800B_0010 - Read/Write VIC2IntEnable: 0x800C_0010 - Read/Write Default: 0x0000_0000 DS785UM1 6-11 Copyright 2007 Cirrus Logic...
Page 174 Clears bits in the VICxIntEnable register. Writing a bit to “1” clears the corresponding bit in the VICxIntEnable register. Any bits written to “0” have no effect. VICxSoftInt SoftInt SoftInt Address: VIC1SoftInt: 0x800B_0018 - Read/Write VIC2SoftInt: 0x800C_0018 - Read/Write 6-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 175 Clears bits in the VICxSoftInt register. Writing a bit to “1” clears the corresponding bit in the VICxSoftInt register. Writing a bit to “0” has no effect. VICxProtection RSVD RSVD Protecti Address: VIC1Protection: 0x800B_0018 - Read/Write VIC2Protection: 0x800C_0018 - Read/Write DS785UM1 6-13 Copyright 2007 Cirrus Logic...
Page 176 VIC_BASE + 0x30. If not, only higher priority interrupts are enabled and there are no higher priority interrupts. Therefore, no more interrupts will occur. If you use the VIC in Vectored Interrupt mode, this is not an issue. 6-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 177 VIC2DefVectAddr: 0x800C_0034 - Read/Write Definition: Default Vector Address Register. The VICxDefVectAddr register contains the default ISR address. Bit Descriptions: DefaultVectorAddr: Contains the address of the default ISR handler. VICxVectAddr0 VICxVectAddr1, VICxVectAddr2, VICxVectAddr3, VICxVectAddr4, VICxVectAddr5, VICxVectAddr6 DS785UM1 6-15 Copyright 2007 Cirrus Logic...
Page 178 VIC1VectAddr13: 0x800B_0134 - Read/Write VIC1VectAddr14: 0x800B_0138 - Read/Write VIC1VectAddr15: 0x800B_013C - Read/Write VIC2VectAddr0: 0x800C_0100 - Read/Write VIC2VectAddr1: 0x800C_0104 - Read/Write VIC2VectAddr2: 0x800C_0108 - Read/Write VIC2VectAddr3: 0x800C_010C - Read/Write VIC2VectAddr4: 0x800C_0110 - Read/Write VIC2VectAddr5: 0x800C_0114 - Read/Write 6-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 179 ISR vector addresses, that is, the addresses of the ISRs for the particular 16 interrupts that are vectored. Bit Descriptions: VectorAddr: Contains ISR vector address. VICxVectCntl0, VICxVectCntl1, VICxVectCntl2, VICxVectCntl3, VICxVectCntl4, VICxVectCntl5, VICxVectCntl6, VICxVectCntl7, VICxVectCntl8, VICxVectCntl9, VICxVectCntl10, VICxVectCntl11, VICxVectCntl12, VICxVectCntl13, VICxVectCntl14, DS785UM1 6-17 Copyright 2007 Cirrus Logic...
Page 180 VIC2VectCntl12: 0x800C_0230 - Read/Write VIC2VectCntl13: 0x800C_0234 - Read/Write VIC2VectCntl14: 0x800C_0238 - Read/Write VIC2VectCntl15: 0x800C_023C - Read/Write Definition: Vector Control Registers. The 32 VICxVectCntl0 through VICxVectCnt15 registers select the interrupt source for the vectored interrupt. 6-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 181 Bit Descriptions: RSVD: Reserved. Unknown During Read. Enables vector interrupt. This bit is cleared to ‘0’ on reset. IntSource: Selects interrupt source by number. You can select any of the 32 interrupt sources. DS785UM1 6-19 Copyright 2007 Cirrus Logic...
Page 182 Vectored Interrupt Controller EP93xx User’s Guide 6-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 183: Timing And Interface
Raster Display should be attached to the AHB and the Arbiter priority should be set to give the Raster Display highest priority. This attachment gets the best bandwidth available for the display, but other system performance will suffer. DS785UM1 Copyright 2007 Cirrus Logic...
Page 184: Table 7-1. Raster Engine Video Mode Output Examples
8, 16, or 24 External SVGA CRT 800 x 600 Analog 8, 16, or External XGA CRT 1024 x 768 Analog 24 bpp SXGA TFT 8, 16, or 24 1280 x 1024 18 or 24 RGB 24-bits DS785UM1 Copyright 2007 Cirrus Logic...
Page 185: Features
For 4 bpp and 8 bpp modes, either multiple or single bit planes may be used to specify blinking pixels by look up in the LUT. This will allow the number of definable blinking pixels to range from all pixel combinations blinking DS785UM1 Copyright 2007 Cirrus Logic...
Page 186: Color Look-Up Tables
Video screen start registers determine the upper left corner of the video screen. Video word addressing in screen memory is from left to right and then from top to bottom. Four-bit pixels packed within video words are organized in DIB format with the left most pixel in the DS785UM1 Copyright 2007 Cirrus Logic...
Page 187: Table 7-2. Byte Oriented Frame Buffer Organization
Byte 9 Byte 8 Byte 0 Byte 3 Byte 6 Byte 9 bit 31 bit 24 bit 23 bit 16 bit 15 bit 8 bit 7 bit 0 Word 0 Word 0 Word 1 Word 2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 188: Frame Buffer Memory Size
7.3.6 Pulse Width Modulated Brightness The circuitry provides a pulse width modulated brightness control output, Bright, that can be used in conjunction with an external resistor and capacitor to provide a DC voltage level for DS785UM1 Copyright 2007 Cirrus Logic...
Page 189: Hardware Cursor
VILOSATI, video FIFO, pixel mux, blink logic, color LUT, RGB mux, output shift logic, grayscale circuitry, hardware cursor logic, YCrCb encoder, and video timing section. A video stream signature generator is also included for built in self testing. DS785UM1 Copyright 2007 Cirrus Logic...
Page 190: Vilosati (Video Image Line Output Scanner And Transfer Interface)
FULL and DS_FULL indicators trigger when either has room for a burst of 8 words (the LSB of FIFOLevel is ignored). For dual and single scan displays, information for the upper left corner of the display begins at the word address stored in the DS785UM1 Copyright 2007 Cirrus Logic...
Page 191: Video Fifo
FIFO location. When the screen is single scan (scanned out as a single progressive image), FIFO data is stored sequentially. The FIFO output data bus is 64 bits wide and can output even and odd DS785UM1 Copyright 2007 Cirrus Logic...
Page 192: Video Pixel Mux
M field in the “PixelMode” register. When Blink to Background mode is enabled, the blink circuitry replaces any blinking pixel with the “BkgrndOffset” register value. Setting this register to the background screen color in 7-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 193: Color Look-Up-Tables
“C” value (color value) in the “PixelMode” register. When in 16-bit 555 or 565 data modes, the pixel data is reformatted to fit into a 24-bit bus. This includes copying the MSBs for the DS785UM1 7-11 Copyright 2007 Cirrus Logic...
Page 194: Pixel Shift Logic
8 pixels per clock modes. Table 7-3 shows output pixel transfer modes based on the shift mode “S” value (shift value) and the color mode “C” value (color value) in the “PixelMode” register: 7-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 195: Table 7-3. Output Pixel Transfer Modes
Table 7-3. Output Pixel Transfer Modes Shift Color Output P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0) Mode Mode Mode single pixel per clock up R(1) R(0) G(1)
Page 196 Table 7-3. Output Pixel Transfer Modes (Continued) Shift Color Output P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0) Mode Mode Mode L G2 L B2 L R1 L G1 L B1 L R0 L G0 L B0 U G2 U B2 U R1 U G1 U B1 U R0 U G0 U B0 dual 2 2/3 pixels per...
Page 197: Grayscale/Color Generator For Monochrome/Passive Low Color Displays
0-7, a 3H (Horizontal) x 3V (Vertical) x 3F (Frame) cube up to a 4H (Horizontal) x 4V (Vertical) x 4F (Frame) cube can be defined. Setting the grayscale matrix values in a channel for full off and full on is very straight forward. DS785UM1 7-15 Copyright 2007 Cirrus Logic...
Page 198: Horz_Cnt3, Horz_Cnt4 Counters
The GrySclLUT combines all of the above information into a single table. In this way, it is possible to define a pixel to be on in all conditions (all HORZ, VERT, and FRAME counts), zero conditions, or any combination. 7-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 199: Grayscale Look-Up Table (Gryscllut)
D15 D14 D13 D12 D11 D10 base+EC D15 D14 D13 D12 D11 D10 base+F0 D15 D14 D13 D12 D11 D10 base+F4 D15 D14 D13 D12 D11 D10 base+F8 D15 D14 D13 D12 D11 D10 base+FC DS785UM1 7-17 Copyright 2007 Cirrus Logic...
Page 200: Gryscllut Timing Diagram
(base + 94) / D9 (base + 94) / D10 (base + 94) / D11 “ “ “ “ (base + 94) / D12 (base + 94) / D13 (base + 94) / D14 7-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 201: Table 7-6. Programming Format
Table 7-6. Programming Format GrySclLU VCNT (lines) Address HCNT Frame (pixels) register address base + 0x00 base + 0x20 base + 0x40 base + 0x60 base + 0x1C base + 0x3C base + 0x5C base + 0x7C DS785UM1 7-19 Copyright 2007 Cirrus Logic...
Page 202: Figure 7-3. Graphics Matrix For 50% Duty Cycle
For this case, we would be right back to the flickering problem shown in Figure 7-4. This would be true if we switched to a checker board pattern and displayed a checker board image or almost any other pattern. 7-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 203: Figure 7-4. Sample Matrix Causing Flickering
3 to eliminate this combination of temporal and spatial distortion. Frame 00 Frame 01 Frame 10 Frame 11 Figure 7-5. Sample Matrix That Avoids Flickering DS785UM1 7-21 Copyright 2007 Cirrus Logic...
Page 204: Figure 7-6. Programming For One-Third Luminous Intensity
The matrix could be filled in as in Figure 7-6. Frame 0 H O R Z Frame 1 Frame 2 Figure 7-6. Programming for One-third Luminous Intensity 7-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 205: Figure 7-7. Creating Bit Patterns That Move To The Right
Value register address base + 0x08 base + 0x28 base + 0x48 base + 0x68 Finally, just for demonstration purposes, a matrix with mixed 3 and 4 count axes is shown in Figure 7-8. DS785UM1 7-23 Copyright 2007 Cirrus Logic...
Page 206: Hardware Cursor
The X and Y locations are compared to the horizontal and vertical counters and trigger the state machine to enable the cursor output overlay. 7-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 207: Table 7-10. Cursor Memory Organization
The cursor hardware will clip the cursor at the bottom of the screen. To prevent cursor distortion, the new Y location value will not be used until the next frame. DS785UM1 7-25 Copyright 2007 Cirrus Logic...
Page 208: Registers Used For Cursor
Two bits select the cursor step size: Step by 1 word or 16 pixels Step by 2 words or 32 pixels Step by 3 words or 48 pixels Step by 4 words or 64 pixels 7-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 209 1. Do not enable/disable the cursor when changing the cursor bitmaps, and 2. When disabling the cursor, change the CursorXYLOc register to point to a blank cursor image. 7.4.9.1.7 CursorDScanLHYLoc Register “CursorDScanLHYLoc” register. DS785UM1 7-27 Copyright 2007 Cirrus Logic...
Page 210: Video Timing
Figure 7-10, "Interlaced Video Signals". Independent horizontal and vertical down counters are used as a reference for all other signals. The synchronization, blanking, and active video control signalling is generated by comparing programmed values to the counters. 7-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 211 Horizontal down counter HCLKSTOTAL -1 HSYNCSTART HSYNCSTOP HCLKSTOP HCLKSTART HACTIVESTRT HACTIVESTOP HSYNCn Horizontal Active Video Horizontal Back Horizontal Front Porch Porch HACTIVE HBLANKn HBLANKSTRT HBLANKSTOP SPCLK DURING Horizontal Figure 7-9. Progressive/Dual Scan Video Signals DS785UM1 7-29 Copyright 2007 Cirrus Logic...
Page 212: Figure 7-10. Interlaced Video Signals
HCLKSTOTAL Horizontal down counter HCLKSTOTAL -1 HSYNCSTART HSYNCSTOP HCLKSTOP HCLKSTART HACTIVESTRT HACTIVESTOP HSYNCn Horizontal Active Video Horizontal Back Horizontal Front Porch Porch HACTIVE HBLANKn HBLANKSTRT HBLANKSTOP SPCLK DURING Horizontal Figure 7-10. Interlaced Video Signals 7-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 213: Setting The Video Memory Parameters
The register settings for this example are: VidScrnPage = 0x1000 (assume SDSEL = 0) ScrnLines = 480 - 1 = 479 = 0x1DF LineLength = (640 x 4bpp / 32) - 1 = 79 = 0x4F DS785UM1 7-31 Copyright 2007 Cirrus Logic...
Page 214: Pixelmode
BlinkRate is the value contained in the “BlinkRate” register 7.4.11.2 Defining Blink Pixels A blink pixel must be defined before the blink logic is applied to a given pixel. The “BlinkPattrn” “PattrnMask” registers are used to define the blink pixels. 7-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 215: Types Of Blinking
M[3:0] bits in the “PixelMode” register: 0000 - Blink Disabled 0001 - AND Blinking. The pixel data is ANDed with the “BlinkMask” register. The modified pixel data will continue through the pipeline. LUT Blink: DS785UM1 7-33 Copyright 2007 Cirrus Logic...
Page 216 1.The LSB is dropped 2.The remaining bits are shifted right by one 3.The MSB is set to ‘0’ 1101 - Bright Single Blinking: The pixel that is identified as a blinking pixel is manipulated: 7-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 217: Color Mode Definition
7.4.12.4 16-bit 555 Color Definition Mode The 16 bits of data is divided into three color planes, where the RED, GREEN, and BLUE each have 5 bits of color definition. The MSB of the 16-bit data is not used. DS785UM1 7-35 Copyright 2007 Cirrus Logic...
Page 218: Registers
Read/Write 24 bits value. 0x8003_0054 PixelMode Read/Write 15 bits Pixel mode definition setup register. Parallel interface write/control 0x8003_0058 ParllIfOut Read/Write 9 bits register. 0x8003_005C ParllIfIn Read/Write 8 + 8 bits Parallel interface read/setup register. 7-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 219 Note: The raster engine registers are intended to be word accessed only. Since the least significant bytes of the address bus are not decoded, byte and half word accesses are illegal and may have unpredictable results. DS785UM1 7-37 Copyright 2007 Cirrus Logic...
Page 220 Figure 7-9 Figure 7-10. VSyncStrtStop RSVD STOP RSVD STRT Address: 0x8003_0004 Default: 0x0000_0000 Definition: Vertical Sync Pulse Start/Stop register Bit Descriptions: RSVD: Reserved - Unknown during read STOP: Stop - Read/Write 7-38 DS785UM1 Copyright 2007 Cirrus Logic...
Page 221 Vertical frame. Please refer to the video signalling timing diagrams in Figure 7-9 Figure 7-10. VACTIVE is an internal block signal. The active video interval is controlled by the logical OR of VACTIVE and HACTIVE. DS785UM1 7-39 Copyright 2007 Cirrus Logic...
Page 222 Vertical frame. Please refer to video signalling timing diagrams in Figure 7-9 Figure 7-10. VBLANKn is an internal block signal. The NBLANK output is a logical AND of NVBLANK and HBLANKn. 7-40 DS785UM1 Copyright 2007 Cirrus Logic...
Page 223 Vertical frame. Please refer to video signalling timing diagrams in Figure 7-9 Figure 7-10. VCLKEN is an internal block signal. The SPCLK output is enabled by the logical AND of VCLKEN and HCLKEN. DS785UM1 7-41 Copyright 2007 Cirrus Logic...
Page 224 Figure 7-9 Figure 7-10. HSyncStrtStop RSVD STOP RSVD STRT Address: 0x8003_0014 Default: 0x0000_0000 Definition: HorizontaL Sync Start/Stop Register Bit Descriptions: RSVD: Reserved - Unknown during read STOP: Stop - Read/Write 7-42 DS785UM1 Copyright 2007 Cirrus Logic...
Page 225 Horizontal line. Please refer to video signalling timing diagrams in Figure 7-9 Figure 7-10. HACTIVE is an internal block signal. The active video interval is controlled by the logical OR of VACTIVE and HACTIVE. DS785UM1 7-43 Copyright 2007 Cirrus Logic...
Page 226 Horizontal line. Please refer to video signalling timing diagrams in Figure 7-9 Figure 7-10. HBLANK is an internal clock signal. The BLANK output is a logical AND of VBLANK and HBLANK 7-44 DS785UM1 Copyright 2007 Cirrus Logic...
Page 227 (starts). This indicates the start of the video clock for the Horizontal frame. Please refer to video signalling timing diagrams in Figure 7-9 Figure 7-10. HCLKEN is an internal clock signal. The SPCLK output is enabled by the logical AND of VCLKEN and HCLKEN. DS785UM1 7-45 Copyright 2007 Cirrus Logic...
Page 228 SDSEL bit held in the “VideoAttribs” register. Not Assigned. Will return written value during a read. VidScrnHPage RSVD PAGE PAGE Address: 0x8003_002C Default: 0x0000_0000 Definition: Video Screen Half Page Register Bit Descriptions: RSVD: Reserved - Unknown during read 7-46 DS785UM1 Copyright 2007 Cirrus Logic...
Page 229 The Lines value written to this field specifies the number of lines to be scanned to the display during normal and half- page mode operation. LineLength RSVD RSVD Address: 0x8003_0034 Default: 0x0000_0000 Definition: Video Line Length Register Bit Descriptions: RSVD: Reserved. Unknown during read. DS785UM1 7-47 Copyright 2007 Cirrus Logic...
Page 230 (specified in 32-bit words) is added to the address for every video line that is scanned to the display. Please see “Memory Setup Example” on page 7-31. This allows the screen width to be smaller than the video image width in SDRAM. 7-48 DS785UM1 Copyright 2007 Cirrus Logic...
Page 231 The Offset value written to this field is added to the address at the end of every other video line if the Offset value is not 0x0. This allows splitting the left and right halves of the display. DS785UM1 7-49 Copyright 2007 Cirrus Logic...
Page 232 When Count > Compare, or Count = Compare, the brightness signal to the BRIGHT pin is ‘0’. When Count < Compare, the brightness signal to the BRIGHT pin is ‘1’. The BRIGHT pin is ‘0’ (zero% brightness) after reset. 7-50 DS785UM1 Copyright 2007 Cirrus Logic...
Page 233 Writing DVERT = ‘1’ forces the values of the defined bit- fields in the VLinesTotal, VSyncStrtStop, VActiveStrtStop, VBlankStrtStop, and VClkStrtStop registers to be doubled (2X programmed value) when used. 0 - Disable 1 - Enable DS785UM1 7-51 Copyright 2007 Cirrus Logic...
Page 234 Parallel Interface Enable - Read/Write 0 - Enable interface for normal display operation 1 - Enable interface for Smart Panel operation Writing PIFEN = ‘1’ redefines the signals on these pins for Smart Panel operation: 7-52 DS785UM1 Copyright 2007 Cirrus Logic...
Page 235 Invert Pixel Clock - Read/Write The value written to this bit selects the active edge of SPCLK on the SPCLK pin: 0 - Pixel data output changes on the rising edge of the clock on the SPCLK pin DS785UM1 7-53 Copyright 2007 Cirrus Logic...
Page 236 Video Sync Enable - Read/Write The value written to this bit selects whether synchronization signals are output to the H_SYNC and V_CSYNC pins, or not: 0 - Video SYNC outputs disabled 1 - Video SYNC outputs enabled 7-54 DS785UM1 Copyright 2007 Cirrus Logic...
Page 237 READ: During a read operation, SWLCK[0] has this meaning: 1 - Unlocked for current bus access 0 - Locked The Read feature of the RasterSWLock register is used for testing the locking function. DS785UM1 7-55 Copyright 2007 Cirrus Logic...
Page 238 ‘on’ state of the pixel is concurrent with the bias frequency. FIFOLevel RSVD RSVD LEVEL Address: 0x8003_0234 Default: 0x0000_0010 Definition: FIFO Refill Level register Bit Descriptions: RSVD: Reserved - Unknown during read LEVEL: Level - Read/Write 7-56 DS785UM1 Copyright 2007 Cirrus Logic...
Page 239 0 - Normal: Blue is the low order bits followed by green and red 1 - Reverse: Red is low order bits followed by green and blue DSCAN: Dual Scan - Read/Write DS785UM1 7-57 Copyright 2007 Cirrus Logic...
Page 240: Table 7-13. Color Mode Definition Table
Table 7-14. Blink Mode Definition Table Blink Mode Blink Mode Disabled Pixels ANDed with Blink Mask Pixels ORed with Blink Mask XORed with Blink Mask Blink to background register Value 7-58 DS785UM1 Copyright 2007 Cirrus Logic...
Page 241: Table 7-15. Output Shift Mode Table
The Graphics Engine has a separate setting for this value, which may or may not be the same. Table 7-16. Bits per Pixel Scanned Out Pixel Mode pixel multiplexer disabled 4 bits per pixel 8 bits per pixel do not use DS785UM1 7-59 Copyright 2007 Cirrus Logic...
Page 242 Writing PIFEN = ‘1’ to VideoAttribs register redefines the signals on these pins for Parallel Interface (Smart Panel) operation: V_CSYNC --> D7 (Smart Panel) HSYNC --> D6 BLANK --> D5 P17 --> D4 7-60 DS785UM1 Copyright 2007 Cirrus Logic...
Page 243 When a write or read cycle is initiated by writing to the RD bit in the ParllIfOut register, the counter begins to count down from this value. DS785UM1 7-61 Copyright 2007 Cirrus Logic...
Page 244 V_CSYNC --> D7 (Smart Panel) HSYNC --> D6 BLANK --> D5 P17 --> D4 P3 --> D3 P[2:0] --> D[2:0] SPCLK --> E Smart Panel R/W and RS signals must be implemented via GPIOs and controlled via software. 7-62 DS785UM1 Copyright 2007 Cirrus Logic...
Page 245 BlinkMask RSVD MASK MASK Address: 0x8003_0044 Default: 0x0000_0000 Definition: Blink Mask register This register is used in conjunction with the BlinkPattrn register to determine which pixels that are fetched from SDRAM are blink pixels. DS785UM1 7-63 Copyright 2007 Cirrus Logic...
Page 246 BlinkMask register. The result is then compared to the blink pattern value that is written to this PATRN field. If the comparison results in a match, the pixel is validated as a blink pixel. 7-64 DS785UM1 Copyright 2007 Cirrus Logic...
Page 247 0 - Bit used for comparison 1 - Bit not used for comparison BkgrndOffset RSVD BGOFF BGOFF Address: 0x8003_0050 Default: 0x0000_0000 Definition: Blink Background Color / Blink Offset value register DS785UM1 7-65 Copyright 2007 Cirrus Logic...
Page 248 The cursor image is 2-bits per pixel, and is stored linearly. The amount of storage space is dependent on the width and height of the cursor. Not Assigned - Will return the written value 7-66 DS785UM1 Copyright 2007 Cirrus Logic...
Page 249 Furthermore, offsetting the reset X location off of the left edge of the screen will allow pixel placement of the cursor off of the screen edge. Not Assigned - Will return the written value DS785UM1 7-67 Copyright 2007 Cirrus Logic...
Page 250 CWID: Cursor Width - Read/Write The Cursor Width value that is written to this field specifies the ‘displayed word width minus one’ of the cursor image: 7-68 DS785UM1 Copyright 2007 Cirrus Logic...
Page 251 SDRAM. When cursor pixels are fetched from SDRAM, they are decoded and displayed as: 00 - Transparent 01 - Invert video stream 10 - CursorColor1 during no blink; CursorBlinkColor1 during blink 11 - CursorColor2 during no blink; CursorBlinkColor2 during blink DS785UM1 7-69 Copyright 2007 Cirrus Logic...
Page 252 When Dual Scan mode is enabled by writing DSCAN = ‘1’ in the PixelMode register, this Cursor Enable bit specifies that some or all of the cursor is located in the upper half of the display. XLOC: Y Location - Read/Write 7-70 DS785UM1 Copyright 2007 Cirrus Logic...
Page 253 Writing a ‘0’ to this bit specifies the opposite. 0 - Hardware cursor not located in lower half of display 1 - Hardware cursor located in lower half of display YLOC: Y Location - Read/Write DS785UM1 7-71 Copyright 2007 Cirrus Logic...
Page 254 When EN = ‘1’ and the 2-bit cursor pixel fetched from SDRAM is ‘11’, CursorBlinkColor1, is used for the ‘on’ part of the blink toggle and CursorColor1, is used for the ‘off’ part of the blink toggle. 7-72 DS785UM1 Copyright 2007 Cirrus Logic...
Page 255 GrySclLUTB - 0x8003_0300 through 0x8003_037C Default: 0x0000_FFFF in offset locations 0x7, 0x15, 0x23, and 0x31 0x0000_0000 in all other locations Definition: Grayscale Look-Up-Tables Bit Descriptions: RSVD: Reserved - Unknown during read FRAME: Frame Counter Selection - Read/Write DS785UM1 7-73 Copyright 2007 Cirrus Logic...
Page 256 Horizontal Counter is used for the current 3- bit pixel value: 0 - use FRAME_CNT3 1 - use FRAME_CNT4 This bit is only defined for address locations GrySclLUTx Base + 0x000 to GrySclLUTx Base + 0x01C. Matrix Position Enable - Read/Write 7-74 DS785UM1 Copyright 2007 Cirrus Logic...
Page 257: Table 7-17. Grayscale Look-Up-Table (Lut)
D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 DS785UM1 7-75 Copyright 2007 Cirrus Logic...
Page 258 Writing a Switch value to this bit selects which of these conditions is present when SSTAT = ‘1’: 0 - RAM0 in video pipeline, RAM1 is accessible from bus 1 - RAM1 in video pipeline, RAM0 is accessible from bus. 7-76 DS785UM1 Copyright 2007 Cirrus Logic...
Page 259 LUT is in the video pipeline, pixel data [23:0] is output from LUT word location ADR[9:2]. Video Signature Registers VidSigRsltVal RSVD SIGVAL Address: 0x8003_0200 Default: 0x0000_0000 Definition: Video Output Signature Result Value register DS785UM1 7-77 Copyright 2007 Cirrus Logic...
Page 260 Writing a ‘1’ to this bit enables the Brightness control output for calculation in the video signature. Writing a ‘0’ to this bit disables the Brightness control output for calculation in the video signature. 7-78 DS785UM1 Copyright 2007 Cirrus Logic...
Page 261 Writing ‘0’s to these bits disables respective pixel bits for calculation in the video signature. VSigStrtStop RSVD STOP RSVD STRT Address: 0x8003_0208 Default: 0x0000_0000 Definition: Vertical Signature Bounds Start/Stop register DS785UM1 7-79 Copyright 2007 Cirrus Logic...
Page 262 (stops). This indicates the end of the signature calculation for a horizontal line. HSIGEN is an internal block signal. The SIG_ENABLE control to the video signature analyzer is enabled by the logical AND of VSIGEN and HSIGEN. STRT: Start - Read/Write 7-80 DS785UM1 Copyright 2007 Cirrus Logic...
Page 263 AND of VSIGCLR and HSIGCLR. The SigClrStr control signal is also routed to an edge trigger capable interrupt on the interrupt controller for use as a programmable secondary raster engine interrupt output. DS785UM1 7-81 Copyright 2007 Cirrus Logic...
Page 264 Raster Engine With Analog/LCD Integrated Timing and Interface EP93xx User’s Guide 7-82 DS785UM1 Copyright 2007 Cirrus Logic...
Page 265: Overview
Since the block transfer features are all in the data path, transfers may be performed with any combination of the previous functions enabled. When combining functions, the precedence is Mask logic first, destination logical combination second, and finally transparency. DS785UM1 Copyright 2007 Cirrus Logic...
Page 266: Copy
Dest = Dest | Src; XOR - This operator is used for pixel bit plane inversion. Dest = Dest ^ Src; (where ^ is an XOR operation) 8.2.1.4 Operation Precedence The order of precedence is: 1. Logical Mask DS785UM1 Copyright 2007 Cirrus Logic...
Page 267: Remapping
The lines may be drawn using solid lines or patterned lines. Accelerated line draw makes it possible to draw a single pixel width line between any two points with sub pixel accuracy. DS785UM1 Copyright 2007 Cirrus Logic...
Page 268: Breshenham Line Draws
P(5,1) P(6,1) P(7,1) P(0,2) P(1,2) P(2,2) P(3,2) P(4,2) P(5,2) P(6,2) P(7,2) P(0,3) P(1,3) P(2,3) P(3,3) P(4,3) P(5,3) P(6,3) P(7,3) P(0,4) P(1,4) P(2,4) P(3,4) P(4,4) P(5,4) P(6,4) P(7,4) P(0,5) P(1,5) P(2,5) P(3,5) P(4,5) P(5,5) P(6,5) P(7,5) DS785UM1 Copyright 2007 Cirrus Logic...
Page 269: Memory Organization For 1 Bit Per Pixel (Bpp)
Raster Engine to map 256 color selections to 24-bit colors. Table 8-4 shows how 8 bpp images are stored in memory as 1 pixel per byte. DS785UM1 Copyright 2007 Cirrus Logic...
Page 270: Memory Organization For 16-Bits Per Pixel
P(3,0) P(2,0) 0x0008 P(5,0) P(4,0) 0x000C P(7,0) P(6,0) 0x0010 P(1,1) P(0,1) 0x0014 P(3,1) P(2,1) 0x0018 P(5,1) P(4,1) 0x001C P(7,1) P(6,1) ....0x0050 P(1,5) P(0,5) 0x0054 P(3,5) P(2,5) 0x0058 P(5,5) P(4,5) 0x005C P(7,5) P(6,5) DS785UM1 Copyright 2007 Cirrus Logic...
Page 271: Memory Organization For 24-Bits Per Pixel
0x001C unused P(7,0)R P(7,0)G P(7,0)B 0x0020 unused P(0,1)R P(0,1)G P(0,1)B ......0x00A0 unused P(0,5)R P(0,5)G P(0,5)B 0x00A4 unused P(1,5)R P(1,5)G P(1,5)B 0x00A8 unused P(2,5)R P(2,5)G P(2,5)B 0x00AC unused P(3,5)R P(3,5)G P(3,5)B DS785UM1 Copyright 2007 Cirrus Logic...
Page 272: Memory Map Access
If a Block Copy starts at pixel 0 and 2 pixels are to be copied, the “BLKSRCWIDTH” register would be loaded with 0x0 (1 word - 1 word = 0x0). The pixels fetched are highlighted in Table 8-9. DS785UM1 Copyright 2007 Cirrus Logic...
Page 273: Example: 24 Bpp (Packed) Mode
1 pixel can reside in a word of memory. This fact requires that the programmer provide the hardware with the exact information of where in a 32-bit word a pixel starts or ends. One register, “SRCPIXELSTRT”, is used for the source DS785UM1 Copyright 2007 Cirrus Logic...
Page 274: Bpp Word Layout
Note:The word count for this example would be: 2 - 1 = 1 words, since P7 ends in the 2nd word. So, WIDTH = 0x1 would be written to the “BLKDESTWIDTH” register. Table 8-14. 4 BPP Memory Layout for Destination Image Address 28 27 24 23 20 19 16 15 12 11 0x0020 0x0024 8-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 275: Bpp Word Layout
0. This makes 0 = 0x0 the value that is used for the SPEL field in the “SRCPIXELSTRT” register. Table 8-17. 16 BPP Memory Layout for Source Image Address 16 15 0x0000 0x0004 0x0008 0x000C DS785UM1 8-11 Copyright 2007 Cirrus Logic...
Page 276: Bpp Mode
The end pixel, P6, is in the word at address 0x006C and has a beginning bit position of 0. This makes 0 = 0x0 the value that is used for the EPEL field in the “DESTPIXELSTRT” register. 8-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 277: Register Usage
“BACKGROUND” register as specified by BG = ‘1’ in “BLOCKCTRL” register. Using DX/DY line draw, the pattern will be more consistent for any line regardless of angle. DS785UM1 8-13 Copyright 2007 Cirrus Logic...
Page 278 -x1) > abs(y2 - y1) Write YINC = (abs(y2 - y1) / abs(x2 - x1)) * 4095). Round to the nearest whole integer value. Write XINC = 0xFFF (4095) 8-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 279: Example Of Breshenham's Algorithm Line Draw
LEN = 640 (pixels) x 1/2 (1 / # of 16-bit pixels in word) = 640 x 1/2 = 320 = 0x140 4. Write SPEL = 0x8 and EPEL = 0x0 to the “DESTPIXELSTRT” register, where: DS785UM1 8-15 Copyright 2007 Cirrus Logic...
Page 280: Block Fill Function
Write the desired pixel-fill value to the MASK field in the “BLOCKMASK” register. The pixel-fill value is dependant on the color depth. 2. Setup DESTPIXELSTRT Register Write the desired values to the SPEL field and the EPEL field in the “DESTPIXELSTRT” register. 8-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 281 For example, a 20-pixels x 10-lines image has a height of 10 lines. So, HEIGHT = 10 - 1 = 9 = 0x9. 6. Setup BLKDESTSTRT Register Write the word-aligned value of the SDRAM address ‘for the beginning of the block fill’ to the “BLKDESTSTRT” register. DS785UM1 8-17 Copyright 2007 Cirrus Logic...
Page 282: Block Copy Function
“DESTLINELENGTH” register. D. Write the value of the WIDTH field to the “BLKSRCWIDTH” register, where WIDTH is the number of 32-bit words, minus 1, that are needed to contain the pixels that 8-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 283: Table 8-21. Words Needed For Six 24-Bit Pixels
D. Write the value of the WIDTH field to the “BLKDESTWIDTH” register, where WIDTH specifies the number of 32-bit words, minus 1, that are needed to contain the pixels that comprise the 1st scan line of the destination image. For an example, please DS785UM1 8-19 Copyright 2007 Cirrus Logic...
Page 284 H. After Step G is complete, write EN = ‘1’ to start the Block Copy function. I. Wait for an interrupt or poll for EN = ‘0’. When the EN bit is cleared to ‘0’, the Block Copy function sequence is done. 8-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 285: Example Of Block Copy
Write EN = ‘1’ to initiate graphics processing I. The final step is to wait for an interrupt or poll for EN = ‘0’. When the EN bit becomes cleared to ‘0’, the Block Copy function is complete. DS785UM1 8-21 Copyright 2007 Cirrus Logic...
Page 286: Registers
Note: Graphics Accelerator registers are intended to be word accessed only. Since the least significant bytes of the address bus are not decoded, byte and half word accesses are illegal and may yield unpredictable results. 8-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 287 For all other modes, the granularity must be a multiple of the pixel size: e.g. in 8 bpp mode, acceptable PEL values are 0x00, 0x08, 0x10, and 0x18. DESTPIXELSTRT RSVD EPEL RSVD SPEL Address: 0x8004_0004 - Read/Write DS785UM1 8-23 Copyright 2007 Cirrus Logic...
Page 288 SDRAM frame buffer. Granularity must be a multiple of the pixel size in all video display modes. For example,.acceptable values in 8 bpp mode are 0x00, 0x08, 0x10, and 0x18. BLKSRCSTRT Address: 0x8004_0008 - Read/Write 8-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 289 The ADR field and the SPEL field in the “DESTPIXELSTRT” register together define the starting pixel’s address in the SDRAM frame buffer of the destination image. Not Assigned - Not used, returns written value DS785UM1 8-25 Copyright 2007 Cirrus Logic...
Page 290 The maximum value for the field is 0xFFE = 4095 words. SRCLINELENGTH RSVD RSVD Address: 0x8004_0014 - Read/Write Default: 0x0000_0000 Mask: 0x0000_0FFF Definition: Block Source Line Length Register Bit Descriptions: RSVD: Reserved - Unknown during read LEN: Length - Read/Write 8-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 291 1st scan line of the destination image. For example, please refer to the note in Section 8.5.2.4 on page 8-12. The maximum value for the field is 0xFFE = 4095 words. DS785UM1 8-27 Copyright 2007 Cirrus Logic...
Page 292 Breshenham algorithm, please refer to BLKDESTHEIGHT Section 8.6.1 on page 8-13. The value of HEIGHT is multiplied by the value of WIDTH in the BLKDESTWIDTH register to determine the number of line draw iterations. 8-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 293 4, where 4 is the number of 8-bit pixels that occupy a word. So, for this example, LEN = 640 / 4 = 160 = 0xA0. Usually the same LEN value is used in both the DESTLINELENGTH register and the SRCLINELENGTH register. DS785UM1 8-29 Copyright 2007 Cirrus Logic...
Page 294: Table 8-23. Pixel Mode Encoding
P value and may be either different or the same. Table 8-23. Pixel Mode Encoding Pixel Mode not defined 4 bit per pixel 8 bits per pixel 8-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 295 BACKGROUND register. Reading this bit returns a valid value only when EN = '1'. REMAP: Pixel Expansion Mapping Function Enable - Read/Write The value of REMAP enables or disables the Pixel Expansion Mapping Function: DS785UM1 8-31 Copyright 2007 Cirrus Logic...
Page 296 Graphics Acceleration function places pixels on the display: For a Block Fill or Block Copy function: DXDIR = ‘1’ - Left in X DXDIR = ‘0’ - Right in X DYDIR = ‘1’ - Up in Y 8-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 297 ‘1’ - Interrupt enabled Initiate Graphics Acceleration Function - Read/Write Read: ‘0’ - Graphics processing completed ‘1’ - Graphics processing in progress Write: ‘0’ - Terminate current graphics processing function ‘1’ - Initiate graphics processing function DS785UM1 8-33 Copyright 2007 Cirrus Logic...
Page 298 16 bpp mode, bits 0-7 are used for 8 bpp mode, and bits 0-3 are used for 4 bpp mode. BLOCKMASK RSVD MASK MASK Address: 0x8004_002C - Read/Write Default: 0x0000_0000 Mask: 0x00FF_FFFF Definition: Block Mask Register Bit Descriptions: RSVD: Reserved - Unknown during read 8-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 299 Bits that are ‘1’ in this field can be used with Line Draw functions to specify a ‘blank space’ in the drawn line. The pixel color value is located in the least significant BPP part of the field for modes less than 24 bpp. DS785UM1 8-35 Copyright 2007 Cirrus Logic...
Page 300 Line Draw function. The maximum value is 4095/4096 and the minimum value is 1/4096. LINEINIT RSVD YINIT RSVD XINIT Address: 0x8004_0038 - Read/Write Default: 0x0000_0000 Mask: 0x0FFF_0FFF Definition: Line Draw Initialization Register 8-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 301 The bit values in this field specify an ‘on’ and ‘off’ pattern that is to be used during a Line Draw function. The pattern will repeat based on the CNT value. A ‘1’ causes a pixel fill from the BLOCKMASK register. DS785UM1 8-37 Copyright 2007 Cirrus Logic...
Page 302 If BG = ‘1’ in the BLOCKCTRL register, a ‘0’ causes a pixel fill from the BACKGROUND register. If BG = ‘0’ in the BLOCKCTRL register, a ‘0’ is transparent. When drawing solid lines, write LINEPATTERN = 0x000F_FFFF. 8-38 DS785UM1 Copyright 2007 Cirrus Logic...
Page 303: Introduction
The Host Interface can be functionally decomposed into the AHB Interface Controller and the Descriptor Processor. The AHB Interface Controller implements the actual connection to the AHB. The controller responds as a AHB bus slave for register programming, and acts as an AHB bus master for data transfers. DS785UM1 Copyright 2007 Cirrus Logic...
Page 304: Reset And Initialization
The only power-down option is to stop the TXCLK and RXCLK by disabling the PHY. 9.1.1.4 Address Space The Address space is mapped as: MACBase + 0x0000 - MACBase + 0x00FF: MAC setup registers. MACBase + 0x0100 - MACBase + 0x011F: MAC configuration registers, only first 4 words used. DS785UM1 Copyright 2007 Cirrus Logic...
Page 305: Mac Engine
FCS. The data after the SFD and before the FCS is supplied by the host as the transmitted data. FCS generation by the MAC may be disabled by setting InhibitCRC bit in the Transmit Frame Descriptor. Refer to Figure 9-2. DS785UM1 Copyright 2007 Cirrus Logic...
Page 306: Figure 9-2. Ethernet Frame / Packet Format (Type Ii Only)
The MAC engine computes the correct FCS, and reports if the received FCS is “good” or “bad”. The data after the SFD and before the FCS is supplied to the host as the received data. The received FCS may also be passed to the host by setting RXCtl.BCRC. DS785UM1 Copyright 2007 Cirrus Logic...
Page 307: Packet Transmission Process
Carrier Deference State Diagram. The Carrier Deference state is independent of entry into the state diagram. The MAC layer may enter the state diagram in any of its five states. The MAC layer exits the Carrier Deference only from the IFG DS785UM1 Copyright 2007 Cirrus Logic...
Page 308: Figure 9-4. Carrier Deference State Diagram
If the deferral process simply allowed the IFG timer to complete, then it is possible for a short Inter Frame Gap to be generated. The 2-part deferral prevents short IFGs. The disadvantage of the 2-part deferral is longer deferrals. In 10BASE-T systems, either deferral method should operate about the same. DS785UM1 Copyright 2007 Cirrus Logic...
Page 309: Transmit Back-Off
CRC computation. If received in error, CRCerror (RStatQ) is set. If CRCerroriE (Interrupt Enable) is set, there is an interrupt associated with CRCerror. The standard CRC conforms to ISO/IEC 8802-3 section 3.2.8. The polynomial for the CRC is: G(x) = x + x + 1 DS785UM1 Copyright 2007 Cirrus Logic...
Page 310: Bit Order
MAC control frames. The third and fourth filters, provide extra optional address match capabilities, which can provide the capability of adding extra individual addresses or of providing two multicast address filters. DS785UM1 Copyright 2007 Cirrus Logic...
Page 311: Hash Filter
If RXCtl.IAHA[0] is set, then a frame with any individual address frame AND passing the hash filter is accepted. An individual address frame is one which has RXCtl.IA[0] = 0. For a frame to pass RXCtl.IAHA[0] it must have RXCtl.IA[0] = 0 and pass the hash. DS785UM1 Copyright 2007 Cirrus Logic...
Page 312: Flow Control
This occurs either immediately, or following the completion of the current transmit frame. If the local transmitter is paused, the pause frame will still be sent, and the pause timer will still be decremented during the frame transmission. 9-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 313: Rx Missed And Tx Collision Counters
The default value of “1” is appropriate for transmitting frames. The MAC won't automatically prepend a preamble when not in transmission mode. Therefore, if the MAC wants to read/write PHY registers, bit PSPRS may be cleared since DS785UM1 9-11 Copyright 2007 Cirrus Logic...
Page 314 IEEE_802.3 standard, and advertise 100/10M full/half duplex available. 2. Write to Basic Mode Control Register (0x00), to enable and restart Auto-Negotiation. 3. Poll bit Auto_Neg_Complete in the BMSR register in the PHY until the Auto-Negotiation is complete. 9-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 315: Descriptor Processor
If the buffer length is set to zero, the descriptor will be ignored, and no status will be posted for the buffer. The buffer index can be used by the Host to keep track DS785UM1 9-13 Copyright 2007 Cirrus Logic...
Page 316: Figure 9-7. Receive Descriptor Format And Data Fragments
Indx k (15) Length k (16) Buffer length register sizes are in bits, 0 to 64 Kbytes and shown in parentheses (). in multiples of 4-bytes Figure 9-7. Receive Descriptor Format and Data Fragments 9-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 317 This should be an integral number of words. If the length is set to zero, the descriptor will be ignored and no status will be posted for the buffer. DS785UM1 9-15 Copyright 2007 Cirrus Logic...
Page 318: Receive Status Queue
No more than 255 status entries may be added in one write. If a number greater than this needs to be written, the write should be broken up into more than one operation (that is, to add 520 status entries: write 255, then write 255, finally write 10). 9-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 319: Figure 9-8. Receive Status Queue
The EOF and EOB bits in the status entry can be used to determine the cause of a status entry. DS785UM1 9-17 Copyright 2007 Cirrus Logic...
Page 320: Receive Status Format
RWE: Received Without Error. The Received Without Error bit indicates that the frame was received without any of the following error conditions: CRCerror, ExtraData, Runt, or Receive Overrun. 9-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 321 CRC Included. This bit is set to one when the CRC has been included in the Receive data buffer. Including or excluding the CRC is controlled by the BufferCRC bit in the RXCtl register. DS785UM1 9-19 Copyright 2007 Cirrus Logic...
Page 322 Frame Length. The frame length field contains the total number of bytes transferred for this frame. For an intermediate status (not end of frame) this is the total number of bytes transferred up through the current data buffer. 9-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 323: Receive Flow
RECV Call Device Driver Receive Receive Frame Descriptor Receive Data Status Queue Queue System Memory PCI Bus Receive Receive Descriptor Descriptor Processor Registers RxDEQ Engine RxSEQ CS 8950 Medium Figure 9-9. Receive Flow Diagram DS785UM1 9-21 Copyright 2007 Cirrus Logic...
Page 324: Receive Errors
(when enabled), system errors, and master or target aborts, these errors will stop receive DMA activity, and require host intervention for recovery. Recovery may be achieved by performing a RxChRes (Bus Master Control) and reinitializing. 9-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 325: Receive Descriptor Data/Status Flow
Process Rx Status, with additional write RxSEQ descriptor count Receive Frame 2 Write Load Rx Status Descriptors Process Rx Status, write RxSEQ Write Rx Status Process Rx Status, write RxSEQ Figure 9-10. Receive Descriptor Data/Status Flow DS785UM1 9-23 Copyright 2007 Cirrus Logic...
Page 326: Receive Descriptor Example
The result of this is that the status queue may be used at a different rate to the descriptor queue, based on the type of traffic and the options selected. 9-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 327: Receive Frame Pre-Processing
In t e r r u p t i f M a s k O K M a s k E n d O f S r e a m i E Figure 9-12. Receive Frame Pre-processing DS785UM1 9-25 Copyright 2007 Cirrus Logic...
Page 328: Transmit Descriptor Processor Queues
No more than 255 descriptors may be added in one write. If a number greater than this needs to be written. the write should be broken up into more than one operation (that is, to add 300 descriptors - first write 255, then write 45). 9-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 329: Figure 9-13. Transmit Descriptor Format And Data Fragments
Data Fragment n Buffer E O F Buffer Buffer Fragment n ( 1 ) Cmd n (4) Index n (15) Length n (12) Length in bytes Figure 9-13. Transmit Descriptor Format and Data Fragments DS785UM1 9-27 Copyright 2007 Cirrus Logic...
Page 330: Transmit Descriptor Format
The CMD field is 4 bits. Only the AF bit is valid. The other fields are reserved. 9.2.3.9 Transmit Descriptor Format Transmit Descriptor Format - First Word Definition: Transmit Descriptor, first word. Contains the base address of the data buffer. 9-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 331 If the incoming frame is received with error, the outgoing frame can be then invalidated. The AF bit is the only valid bit in the CMD field. RSVD: Reserved. Unknown During Read. DS785UM1 9-29 Copyright 2007 Cirrus Logic...
Page 332: Transmit Status Queue
(same value as the base address). The Host needs to ensure that in operation there is always room in the status queue for any transmit frame which is enqueued in the transmit descriptor queue. 9-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 333: Figure 9-15. Transmit Status Queue
Current Frame Status Transmit Status Current Next Status Position Address (TxSCA)(32) Status m 31 30 Frame Status (15) Buffer Index (15) TxWE = Transmitted Without Error TxFP = Transmit Frame Processed Figure 9-15. Transmit Status Queue DS785UM1 9-31 Copyright 2007 Cirrus Logic...
Page 334: Transmit Status Format
Excess Collisions. The excessive collision bit is set when the frame failed to transmit due to excessive collisions. This may either be due to one or sixteen collisions dependent on the OneColl bit in the transmit descriptor. 9-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 335 Transmit Buffer Index. The transmit buffer index is a copy of the transmit buffer index from the first descriptor of a transmit frame. This is provided as an aid to the Host software in keeping track of the transmit buffers. DS785UM1 9-33 Copyright 2007 Cirrus Logic...
Page 336: Transmit Flow
TX_Complete XMIT Call Device Driver Tx Descriptor Transmit Frame Tx Status Queue Data Queue System Memory PCI Bus Transmit Transmit Descriptor Descriptor Processor Registers TxDEQ Engine CS 8950 Medium Figure 9-16. Transmit Flow Diagram 9-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 337: Transmit Errors
Descriptor Processor registers to point to the start of the failed frame and re-initialize. This will cause the MAC to reattempt the failed frame and allows the order of frame transmission to be maintained. DS785UM1 9-35 Copyright 2007 Cirrus Logic...
Page 338: Transmit Descriptor Data/Status Flow
Data Write TxDEQ with valid descriptor count Read Tx Descriptors Read Tx Data Write Send Frame 2 Tx Status Process Tx Status Write Tx Status Process Tx Status Figure 9-17. Transmit Descriptor Data/Status Flow 9-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 339: Interrupts
12.Set BMCtl.TxEn which clears the TXDEnq and initializes internal pointers to the queues. No bus master activity is triggered by the enable because the enqueue register is zero. 13.Set required interrupt mask and global interrupt mask (IntEn, GlIntMsk). DS785UM1 9-37 Copyright 2007 Cirrus Logic...
Page 340: Interrupt Processing
9.2.5.4 Other Processing The upper three bytes of the Interrupt Status register provide the specific information related to the “Other” bit in the LSB. There are a number of bits that relate to the descriptor queues. 9-38 DS785UM1 Copyright 2007 Cirrus Logic...
Page 341: Transmit Restart Process
TXStsQCurAdd to this address. This can be the start of the status queue, as all existing status entries have been processed. 9. Set TxEn in BMCtl. This will cause the Transmit Descriptor Processor to reinitialize. DS785UM1 9-39 Copyright 2007 Cirrus Logic...
Page 342: Registers
0x8001_009C RXDEnq MAC Receive Descriptor Enqueue Register 0x8001_00A0 RXStsQBAdd MAC Receive Status Queue Base Address Register 0x8001_00A4 RXStsQBLen MAC Receive Status Queue Base Length Register RXStsQCurL 0x8001_00A6 MAC Receive Status Queue Current Length Register 9-40 DS785UM1 Copyright 2007 Cirrus Logic...
Page 343 MAC Receive Header Length Register 0x8001_0100 - Reserved 0x8001_010C 0x8001_4000 - MACFIFO MAC FIFO RAM 0x8001_FFFF Control Register Description RXCtl RSVD PauseA RxFCE1 RxFCE0 BCRC SRxON RSVD RCRCA IAHA RSVD Address: 0x8001_0000 - Read/Write DS785UM1 9-41 Copyright 2007 Cirrus Logic...
Page 344: Table 9-4. Individual Accept, Rxflow Control Enable And Pause Accept Bits
Host as regular frames. When clear, the frames are discarded. The handling of MAC Control frames depends on the Pause Accept bit as well as the appropriate Individual Accept and RxFlow Control Enable bits, as follows. 9-42 DS785UM1 Copyright 2007 Cirrus Logic...
Page 345 Multicast Accept. When set, received frames are accepted if the DA, when hashed, matches one of the hash table bits, and the frame is a multicast frame (first bit of destination address = 1). See Descriptor Processor Transmit Registers. DS785UM1 9-43 Copyright 2007 Cirrus Logic...
Page 346 When the host changes the destination filter, it is possible that a frame will be missed while SerRxON is clear. TXCtl RSVD RSVD DefDis ICRC TxPD OColl STxON Address: 0x8001_0004 - Read/Write Chip Reset: 0x0000_0000 9-44 DS785UM1 Copyright 2007 Cirrus Logic...
Page 347 Individual Address number 6 Source Address Individual Address number 1 Type Field Type Field defined in the Flow Control Format register0 Opcode 0x0001 Pause Time Pause Field defined in the Flow Control Format register Pad fill DS785UM1 9-45 Copyright 2007 Cirrus Logic...
Page 348 0 = Get 32 ones before SFD. Note: The user must check the datasheet of the PHY being used in the design. If the PHY needs a preamble for reading/writing to/from PHY registers, the PSPRS must be cleared (set to 9-46 DS785UM1 Copyright 2007 Cirrus Logic...
Page 349 For reliable operation a software reset should be issued when the MII loopback bit is changed. DS785UM1 9-47 Copyright 2007 Cirrus Logic...
Page 350 0x08 Debug FIFO Data 0x98 Receive Data FIFO Pointers 0x9C Transmit Data FIFO Pointers 0xA0 Receive Status FIFO Pointers 0xA4 Transmit Status FIFO Pointers 0xA8 Receive Descriptor FIFO Pointers 0xAC Transmit Descriptor FIFO Pointers 9-48 DS785UM1 Copyright 2007 Cirrus Logic...
Page 351 Diagnostic Address register. For debug only. Bit Descriptions: DATA: Internal register data value. Address: 0x8001_0040 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: General Timer Register DS785UM1 9-49 Copyright 2007 Cirrus Logic...
Page 352 While the timer is non zero, no new transmit frames are started. The decrement time depends on the speed, but always corresponds to the duration of a 64 byte minimum packet. 9-50 DS785UM1 Copyright 2007 Cirrus Logic...
Page 353 The format of a transmit pause frame is: 1. Destination address = Individual address[6] (6 bytes) 2. Source address = Individual address[0] (6 bytes) 3. Type field = MAC Control Type (2bytes) 4. Opcode = 0x0001 (2bytes) DS785UM1 9-51 Copyright 2007 Cirrus Logic...
Page 354: Table 9-5. Address Filter Pointer
These secondary addresses are only used for qualifying the destination addresses of receive frames. These locations are not implemented This address is used as the destination address of transmit pause frames This block comprises the hash table used for qualifying the destination of receive frames. 9-52 DS785UM1 Copyright 2007 Cirrus Logic...
Page 355 The least significant byte of the Individual Address corresponds to the first byte of the address on the serial interface, with the least significant bit of the byte corresponding to the first bit on the serial interface. Bit Descriptions: IAD: Individual Address. DS785UM1 9-53 Copyright 2007 Cirrus Logic...
Page 356 If an individual address frame passes the hash test and the IAHA bit is set, the frame passes the destination filter. If a group address frame passes the hash test and the MA bit set, the frame passes the destination filter. Bit Descriptions: HTb: Hash Table entries. 9-54 DS785UM1 Copyright 2007 Cirrus Logic...
Page 357 The register is cleared automatically following a read and writing to the register will have no effect. RXMissCnt RSVD Address: 0x8001_0074 - Read Only Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 DS785UM1 9-55 Copyright 2007 Cirrus Logic...
Page 358 CRC. When the most significant bit of the count is set, an optional interrupt may be generated. The register is cleared automatically following a read, writing to the register will have no effect. 9-56 DS785UM1 Copyright 2007 Cirrus Logic...
Page 359 Section 9.1.4 on page 9--7. IntEn RSVD / RWIE RxMIE RxBIE RxSQIE TxLEIE ECIE TxUHIE RSVD MOIE TxCOIE RxROIE RSVD RSVD MIIIE PHYSIE RSVD SWIE RSVD TSQIE REOFIE REOBIE RHDRIE DS785UM1 9-57 Copyright 2007 Cirrus Logic...
Page 360 MAC runs out of data before the full transmitted length, then there is a transmit underrun. If the MAC is programmed to halt in this condition (Bus Master Control), setting TxUnderrunHaltiE will cause an interrupt to be generated. 9-58 DS785UM1 Copyright 2007 Cirrus Logic...
Page 361 REOFIE, REOBIE, RHDRIE: Setting all three bits causes interrupts to be generated whenever a receive-end-of-frame status, or a receive-end-of-buffer status, or a receive-header status is written to the receive status queue. DS785UM1 9-59 Copyright 2007 Cirrus Logic...
Page 362 6 bytes of FFh followed by 8 repetitions of the Individual Address and be a legal frame (legal length and good CRC). 9-60 DS785UM1 Copyright 2007 Cirrus Logic...
Page 363 When a transmit collision occurs, the transmit collision count is incremented. When the MSB of the count is set the TxCOI bit in the Interrupt Status Register is set. If the TxCOIE bit is set, an interrupt will be generated. DS785UM1 9-61 Copyright 2007 Cirrus Logic...
Page 364 This bit can only be set if bit 2 (REOFIE), bit 1 (REOBIE) and bit 0 (RHDRIE) of the Interrupt Enable (IntEn) register are set (enabled). GlIntSts RSVD RSVD Address: 0x8001_0060 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 9-62 DS785UM1 Copyright 2007 Cirrus Logic...
Page 365 Reserved. Unknown During Read. INT: Global interrupt mask bit. When set, any interrupt enabled by the Interrupt Enable Register will set the Global Interrupt Status interrupt bit. When clear, no interrupts will reach the processor. DS785UM1 9-63 Copyright 2007 Cirrus Logic...
Page 366 MACint signal to the interrupt controller is active. GlIntFrc RSVD RSVD Address: 0x8001_006C - Write Only Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Global Interrupt Force Register. This register allows software to generate an interrupt. 9-64 DS785UM1 Copyright 2007 Cirrus Logic...
Page 367 MII command data port. Bit Descriptions: RSVD: Reserved. Unknown During Read. OPcode. This Opcode field defines the type of operation to be performed to the appropriate PHY register. 10 - Read register 01 - Write register DS785UM1 9-65 Copyright 2007 Cirrus Logic...
Page 368 MII Data Register. This register contains the 16 bit data word that is either written to or read from the appropriate PHY register. MIISts RSVD RSVD BUSY Address: 0x8001_0018 - Read Only Chip Reset: 0x0000_0000 9-66 DS785UM1 Copyright 2007 Cirrus Logic...
Page 369 BMCtl RSVD RSVD TxChR TxDis TxEn RSVD EEOB RSVD RxChR RxDis RxEn Address: 0x8001_0080 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: 0x0000_0000 Definition: Bus Master Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 9-67 Copyright 2007 Cirrus Logic...
Page 370 When transfers have been halted, the TxAct bit (Bus Master Status) is clear. TxDis is an act-once-bit and will clear immediately. 9-68 DS785UM1 Copyright 2007 Cirrus Logic...
Page 371 When the transfers are halted, the RxAct bit (Bus Master Status) is cleared. This bit is an act-once-bit and will clear immediately. DS785UM1 9-69 Copyright 2007 Cirrus Logic...
Page 372 Transfer Pending. When the Manual Transfer bit (BMCtl) is set, the Transfer Pending bit is set, until all internal FIFOs have either been active for a DMA transfer, or have been determined to be inactive (that is, empty transmit status FIFO). 9-70 DS785UM1 Copyright 2007 Cirrus Logic...
Page 373 Current Descriptor Address whenever the end of the descriptor queue is reached. The base address should be set at initialization time and must be set to a word aligned memory address. Bit Descriptions: RDBA: Receive Descriptor Base Address. DS785UM1 9-71 Copyright 2007 Cirrus Logic...
Page 374 Bit Descriptions: RSVD: Reserved. Unknown During Read. RDBL: Receive Descriptor Base Length. RXDQCurLen RSVD RDCL Address: 0x8001_0096 - Read/Write. Note half word alignment. Chip Reset: 0x0000_0000 Soft Reset: Unchanged 9-72 DS785UM1 Copyright 2007 Cirrus Logic...
Page 375 Intermediate values in this register will not necessarily align to descriptor boundaries, nor directly effect the current descriptor in use because several descriptors may be buffered inside the MAC. Bit Descriptions: RDCA: Receive Descriptor Current Address. DS785UM1 9-73 Copyright 2007 Cirrus Logic...
Page 376 Descriptor Increment, the new Value will be 0x0A. If the controller then reads two descriptors, the Value will be 0x08. Bit Descriptions: RSVD: Reserved. Unknown During Read. RDV: Receive Descriptor Value. RDI: Receive Descriptor Increment. RXBCA RBCA RBCA Address: 0x8001_0088 - Read/Write 9-74 DS785UM1 Copyright 2007 Cirrus Logic...
Page 377 Address whenever the end of the status queue is reached. The base address should be set at initialization time and must be set to a word aligned memory address. Bit Descriptions: RSQBA: Receive Status Queue Base Address. DS785UM1 9-75 Copyright 2007 Cirrus Logic...
Page 378 Bit Descriptions: RSVD: Reserved. Unknown During Read. RSQBL: Receive Status Queue Base Length. RXStsQCurLen RSVD RSQCL Address: 0x8001_00A6 - Read/Write. Note half word alignment. Chip Reset: 0x0000_0000 Soft Reset: Unchanged 9-76 DS785UM1 Copyright 2007 Cirrus Logic...
Page 379 Status Address whenever the end of the status queue is reached. The base address should be set at initialization time and must be set to a word aligned memory address. Bit Descriptions: RSQCA: Receive Status Queue Current Address. DS785UM1 9-77 Copyright 2007 Cirrus Logic...
Page 380 Value will be 0x0A. If the controller then reads two descriptors, the Value will be 0x08. Bit Descriptions: RSVD: Reserved. Unknown During Read. RSV: Receive Status Value. RSI: Receive Status Increment. RXHdrLen RSVD RHL2 RSVD RHL1 Address: 0x8001_00EC - Read/Write 9-78 DS785UM1 Copyright 2007 Cirrus Logic...
Page 381 This address is used by the MAC to reload the Transmit Current Descriptor Address whenever the end of the descriptor queue is reached. The base address should be set at initialization time and must be set to a word aligned memory address. DS785UM1 9-79 Copyright 2007 Cirrus Logic...
Page 382 Bit Descriptions: RSVD: Reserved. Unknown During Read. TDBL: Transmit Descriptor Base Length. TXDQCurLen RSVD TDCL Address: 0x8001_00B6 - Read/Write. Note half word alignment. Chip Reset: 0x0000_0000 9-80 DS785UM1 Copyright 2007 Cirrus Logic...
Page 383 Intermediate values in this register will not necessarily align to descriptor boundaries, nor directly effect the current descriptor in use because several descriptors may be buffered inside the MAC. Bit Descriptions: TDCA: Transmit Descriptor Current Address. DS785UM1 9-81 Copyright 2007 Cirrus Logic...
Page 384 Transmit Descriptor Increment, the new Value will be 0x0A. If the controller then reads two descriptors, the Value will be 0x08. Bit Descriptions: RSVD: Reserved. Unknown During Read. TDV: Transmit Descriptor Value. TDI: Transmit Descriptor Increment. TXStsQBAdd TSQBA TSQBA Address: 0x8001_00C0 - Read/Write Chip Reset: 9-82 DS785UM1 Copyright 2007 Cirrus Logic...
Page 385 Length defines the actual number of bytes in the transmit status queue. The length should be set at initialization time and must define an integral number of transmit statuses. Bit Descriptions: RSVD: Reserved. Unknown During Read. TSQBL: Transmit Status Queue Base Length. DS785UM1 9-83 Copyright 2007 Cirrus Logic...
Page 386 The register should not normally be written. Bit Descriptions: RSVD: Reserved. Unknown During Read. TSQCL: Transmit Status Queue Current Length. TXStsQCurAdd RSQCA TSQCA Address: 0x8001_00C8 - Read/Write Chip Reset: 0x0000_0000 Soft Reset: Unchanged 9-84 DS785UM1 Copyright 2007 Cirrus Logic...
Page 387 The lower 2 bits of each threshold are always zero. Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. RDHT: Receive Data Hard Threshold. DS785UM1 9-85 Copyright 2007 Cirrus Logic...
Page 388 MAC, such as no active transmit descriptor. The lower two bits of the thresholds are always zero. Bit Descriptions: RSVD: Reserved. Unknown During Read. TDHT: Transmit Data Hard Threshold. 9-86 DS785UM1 Copyright 2007 Cirrus Logic...
Page 389 MAC, such as the RXStsEnq register being equal to zero. The lower two bits of the thresholds are always zero. Bit Descriptions: RSVD: Reserved. Unknown During Read. RSHT: Receive Status Hard Threshold. RSST: Receive Status Soft Threshold. DS785UM1 9-87 Copyright 2007 Cirrus Logic...
Page 390 The lower two bits of the thresholds are always zero. Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. TSHT: Transmit Status Hard Threshold. TSST: Transmit Status Soft Threshold. 9-88 DS785UM1 Copyright 2007 Cirrus Logic...
Page 391 MAC, such as a RXDEnq equal to zero. The lower two bits of the thresholds are always zero. Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. RDHT: Receive Status Hard Threshold. DS785UM1 9-89 Copyright 2007 Cirrus Logic...
Page 392 MAC, such as a TXDEnq equal to zero. The lower two bits of the thresholds are always zero. Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. TDHT: Transmit Descriptor Hard Threshold. 9-90 DS785UM1 Copyright 2007 Cirrus Logic...
Page 393 The status written for the frame will indicate the length error, and further frames will continue as normal, (the Receive Descriptor Processor will not halt). DS785UM1 9-91 Copyright 2007 Cirrus Logic...
Page 394 FIFO before a frame will start transmission on the serial interface. This value is primarily of concern when the transmit frame is spread across multiple descriptors and the first descriptors define small amounts of data. 9-92 DS785UM1 Copyright 2007 Cirrus Logic...
Page 395: Introduction
10.1.1 DMA Features List DMA specific features are: • Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx and 5 Rx). • Two dedicated channels for Memory-to-Memory (M2M) and Memory-to-External Peripheral Transfers (external M2P/P2M). DS785UM1 10-1 Copyright 2007 Cirrus Logic...
Page 396: Managing Data Transfers Using A Dma Channel
Status bits will indicate if the actual byte count is equal to the programmed limit. Completion of transfer will cause a DMA interrupt on that channel and rollover to the “other” buffer descriptor, if configured. 10-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 397: Dma Operations
For this transfer type, the DMA first fills the internal 16-byte data bay by initiating read accesses on the source bus. It then empties the data from the data bay to the destination bus by initiating write accesses. • Memory locations related to IDE or SSP. DS785UM1 10-3 Copyright 2007 Cirrus Logic...
Page 398: Memory-To-Peripheral Channels
If RxEnd signals an error in receive data, and if the ICE bit (Ignore Channel Error) is set, then the DMA continues transfers as normal. The RxEnd is asserted by the peripheral coincident with the last good data before the overrun 10-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 399: M2M Ahb Master Interface Functional Description
4. If the number of bytes is less than 4, then byte accesses are performed until the remainder of the data has been transferred. DS785UM1 10-5 Copyright 2007 Cirrus Logic...
Page 400: Hardware Trigger Mode For Internal Peripherals (Ssp And Ide) And For External Peripherals Without Handshaking Signals
In order to build the quad word bursts from the single bytes received from the peripheral, the DMA controller uses the Rx Burst Packers. To decompose the quad word bursts into byte transfers to the peripherals the Tx Burst Un-Packers are used. 10-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 401: Internal M2P/P2M Dma Functional Description
DMA_IDLE ENABLE DISABLE CE.ABORT.ICE DISABLE DISABLE DMA_NEXT DMA_STALL Buffer End or Buffer End or CE.ICE.ABORT CE.ICE Write Write Base Base Address Address DMA_ON Figure 10-1. DMA M2P/P2M Finite State Machine DS785UM1 10-7 Copyright 2007 Cirrus Logic...
Page 402 (buffer Y). It will generate an interrupt (NFBint) to signal to the processor that it is switching over to a new buffer and that the old buffer descriptor (buffer X) is available to be updated. Data transfers occur in this state. 10-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 403: Data Transfer Initiation And Termination
• Bursting across buffers cannot be carried out in either transmit or receive directions. The reason is that buffer pairs may not be contiguous, as required by HTRANS SEQ transfer type (where address = address of previous transfer + size in bytes). DS785UM1 10-9 Copyright 2007 Cirrus Logic...
Page 404: M2M Dma Functional Description
No STALL interrupt is generated for this condition. The DMA M2M Control FSM enters the DMA_STALL state when a memory-to-memory transfer has completed successfully. The DONE and STALL interrupts are generated for this condition, if enabled. 10-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 405 The DMA M2M Control FSM stays in this state until the data transfer to memory has completed, that is, the data bay is emptied. Data transfers, to memory or external peripheral (depending on the CONTROL.TM bits), occur in this state. DS785UM1 10-11 Copyright 2007 Cirrus Logic...
Page 406: M2M Buffer Control Finite State Machine
When the DMA Buffer FSM transitions from DMA_BUF_NEXT to DMA_BUF_ON state, the NFB (Next Frame Buffer) interrupt is generated. This signals to software that rollover is occurring to the other buffer and also that one of the BCRx registers is now free for update 10-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 407: Data Transfer Initiation
• NFB interrupt is generated when FSM moves to DMA_BUF_ON state, signalling that • Buffer0 is now free for update. 10.1.10.3 Data Transfer Initiation Memory-to-memory transfers require a read-from and a write-to memory to complete each transfer. DS785UM1 10-13 Copyright 2007 Cirrus Logic...
Page 408 DREQ from the external peripheral before initiating a transfer. The DMA Controller initiates memory-to-memory transfers in the transmit direction (that is, from DMA to memory/external bus) under the following circumstances: 10-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 409: Data Transfer Termination
DEOT from the device while it is transferring to/from the last buffer (that is, no other buffer has been set up), or when the BCR registers of both buffer descriptors has reached zero. DS785UM1 10-15 Copyright 2007 Cirrus Logic...
Page 410: Memory Block Transfer
DREQP[0] of the CONTROL register), a request becomes pending. The DMA synchronizes the latched DREQ input using 2 HCLK flip-flops for metastability protection. The DREQS status bit is set to indicate that a request is pending. 10-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 411: Dma Data Transfer Size Determination
Data transfer size flexibility is guaranteed by allowing the start address of a DMA transfer to be aligned to any arbitrary byte boundary since this is the case for the 10 internal byte-wide M2P/P2M channels and for the 2 M2M channels when used in software initiated mode. DS785UM1 10-17 Copyright 2007 Cirrus Logic...
Page 412: Hardware-Initiated M2M Transfers
(and not the DMA). 10.1.12 Buffer Descriptors A “buffer” refers to the area in system memory that is characterized by a buffer descriptor, that is, a start address and the length of the buffer in bytes. 10-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 413: Internal M2P/P2M Channel Rx Buffer Descriptors
M2P Ch 1 M2M Ch 1 M2P Ch 2 M2P Ch 0 M2P Ch 3 M2P Ch 1 M2P Ch 4 M2P Ch 2 M2P Ch 5 M2P Ch 3 M2P Ch 6 M2P Ch 4 DS785UM1 10-19 Copyright 2007 Cirrus Logic...
Page 414: Registers
0x8000_0240 -> 0x8000_027C M2P Channel 4 Registers (Tx) 0x8000_0240 0x8000_0280 -> 0x8000_02BC M2P Channel 7 Registers (Rx) 0x8000_0280 0x8000_02C0 -> 0x8000_02FC M2P Channel 6 Registers (Tx) 0x8000_02C0 0x8000_0300 -> 0x8000_033C M2P Channel 9 Registers (Rx) 0x8000_0300 10-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 415: Internal M2P/P2M Channel Register Map
Channel Base Address + 0x003C Reserved Note:See Table 10-3 for Channel Base Addresses Note:* - write this location once to clear the interrupt (see Interrupt register description for which bits this rule applies to). DS785UM1 10-21 Copyright 2007 Cirrus Logic...
Page 416 Setting this bit to 1 enables the channel, clearing this bit disables channel, and causes the remaining unpacker/packer data to be discarded. The channel must always be enabled before writing the Base address register. 10-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 417 Port 0 and Channel 2 will not function correctly. The PPALLOC register must be written to before a channel is enabled. If this is not done, then the default allocation of the ports will be used. DS785UM1 10-23 Copyright 2007 Cirrus Logic...
Page 418: Table 10-5. Ppalloc Register Bits Decode For A Transmit Channel
Port allocated on reset 0000 PORT 0 0000 PORT 1 0001 PORT 2 0001 PORT 3 0010 PORT 4 0010 PORT 5 0011 PORT 6 0011 PORT 7 0100 PORT 8 0100 PORT 9 10-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 419 DMA Channel detects an error in the data stream. The peripherals signal this error by ending the current transfer with a TxEnd/RxEnd error response. The interrupt is cleared by writing either a “1” or a “0” to this bit. DS785UM1 10-25 Copyright 2007 Cirrus Logic...
Page 420 1 - The last buffer transfer terminated with an error. BYTES: This is the number of valid DMA data currently stored by the channel in the DMA Controller in packer or unpacker. Usually used for test/debug. 10-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 421 If CurrentState = DMA_ON and NextBuffer = 0 then Buffer1 is the active buffer. If CurrentState = DMA_NEXT and NextBuffer = 0 then Buffer0 is the active buffer. If CurrentState = DMA_NEXT and NextBuffer =1 then Buffer1 is the active buffer. DS785UM1 10-27 Copyright 2007 Cirrus Logic...
Page 422 DMA transfers may also be stopped with the TxEnd/RxEnd signals from the peripheral, where the REMAIN register is non-zero at the end of transfer, allowing software to determine the last valid data in a buffer. 10-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 423 = “0” or “1”. Base address for the current and next DMA transfer. Loaded with start address after enabling the DMA Channel, the latter event required to take the Channel State machine into the STALL state, the former event required to enter the ON State. DS785UM1 10-29 Copyright 2007 Cirrus Logic...
Page 424: Table 10-8. Ppalloc Register Reset Values
Channel Base Address + 0x0010 BCR0 Channel Base Address + 0x0014 BCR1 Channel Base Address + 0x0018 SAR_BASE0 Channel Base Address + 0x001C SAR_BASE1 Channel Base Address + 0x0020 Reserved Channel Base Address + 0x0024 SAR_CURRENT0 10-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 425 (this is the default setting). In order to use this feature the SAR_BASEx and DAR_BASEx registers must contain word-aligned addresses - the DMA will ignore the 2 LSB’s DS785UM1 10-31 Copyright 2007 Cirrus Logic...
Page 426 M2M transfers, where HREQ stays asserted throughout the transfer. For transfer to/from external devices, HREQ is released after every transfer, and so bandwidth control is not needed. The BWC bits are ignored when in external DMA transfer mode. 10-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 427: Table 10-9. Bwc Decode Values
10 - Word (32 bits) 11 - Not used For word accesses the lower 2 bits of the source/destination address are ignored. For half-word accesses the lower bit of the source/destination address is ignored. DS785UM1 10-33 Copyright 2007 Cirrus Logic...
Page 428 DREQ. 00 - DREQ is active low, level sensitive. 01 - DREQ is active high, level sensitive. 10 - DREQ is active low, edge sensitive. 11 - DREQ is active high, edge sensitive. 10-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 429 SMC.If the acknowledge from the SMC takes too long to arrive, the processor can still cancel the counter stall by writing the CONTROL register. INTERRUPT RSVD RSVD NFBint DONEInt STALLInt Address: Channel Base Address + 0x0004 - Read/Write DS785UM1 10-35 Copyright 2007 Cirrus Logic...
Page 430 The interrupt is not generated for a single-buffer transfer. In software triggered M2M mode, servicing of the NFB interrupt is dependent on the system level AHB arbitration since the DMA’s HREQ (AHB request) may be continuously held high. 10-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 431 IDLE state, only when entered from MEM_WR State. The STALL state can be cleared by: •Setting the START bit •An external peripheral requesting service (depending on transfer mode) •Disabling the DMA channel •A request from SSP or IDE DS785UM1 10-37 Copyright 2007 Cirrus Logic...
Page 432 11 - Terminal Count has been reached for both buffer descriptors. The TCS status bit for a buffer descriptor is cleared when the BCR register of that buffer descriptor has been programmed with a new value. 10-38 DS785UM1 Copyright 2007 Cirrus Logic...
Page 433 Then the DMA switches over to using buffer1 at which time the NFB interrupt is generated and software reads the NextBuffer status bit to determine what buffer descriptor is now free for update - in this case it is buffer0. DS785UM1 10-39 Copyright 2007 Cirrus Logic...
Page 434 DREQS bit. If an edge is detected on DREQ when no previous request is still pending in the DMA (that is, DREQS clear), then the DREQS bit is set by the DMA 10-40 DS785UM1 Copyright 2007 Cirrus Logic...
Page 435 Writing to a BCRx register causes a next buffer update, that is, only the BCR of the buffer descriptor has to be written to in order to use that buffer since the SAR_BASEx and DAR_BASEx registers do not have to be continuously updated. DS785UM1 10-41 Copyright 2007 Cirrus Logic...
Page 436 “other” buffer is being carried out (thus reducing software latency impact). When transferring from external device to memory, the SAR_BASEx will contain the base address of the memory mapped device. 10-42 DS785UM1 Copyright 2007 Cirrus Logic...
Page 437 SAR_CURRENTx SAR_CURRENTx SAR_CURRENTx Address: SAR_CURRENT0: Channel Base Address + 0x0024 - Read Only SAR_CURRENT1: Channel Base Address + 0x0028 - Read Only Definition: This is the Channel Current Source Address Register. DS785UM1 10-43 Copyright 2007 Cirrus Logic...
Page 438 Following completion of a transfer from a buffer, the post-incremented address is stored in this register so that a software service routine can detect the point in the buffer at which transfer was terminated. DMAGlInt RSVD RSVD 10-44 DS785UM1 Copyright 2007 Cirrus Logic...
Page 439: Table 10-10. Dma Global Interrupt (Dmaglint) Register
M2P Channel 7 Interrupt M2P Channel 4 Interrupt M2P Channel 5 Interrupt M2P Channel 2 Interrupt M2P Channel 3 Interrupt M2P Channel 0 Interrupt M2P Channel 1 Interrupt DMAChArb RSVD RSVD CHARB Address: 0x8000_0380 - Read/Write DS785UM1 10-45 Copyright 2007 Cirrus Logic...
Page 440 Memory-to- Peripheral channels having a higher priority than Memory- to-Memory channels. This bit can be set to “1” to reverse the default order, that is, giving M2M transfers a higher priority than internal M2P. 10-46 DS785UM1 Copyright 2007 Cirrus Logic...
Page 441: Chapter 11. Universal Serial Bus Host Controller
Figure 11-6. 11.2 Overview Figure 11-1 shows four main focus areas of a USB system. These areas are: • Client Software/USB Driver • Host Controller Driver (HCD) • Host Controller (HC) • USB Device. DS785UM1 11-1 Copyright 2007 Cirrus Logic...
Page 442: Data Transfer Types
Periodic transfers are interrupt and isochronous since they are scheduled to run at periodic intervals. Nonperiodic transfers are control and bulk since they are not scheduled to run at any specific time, but rather on a time-available basis. 11-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 443: Host Controller Interface
Host Controller Communications Area Registers Interrupt 0 Mode Interrupt 1 HCCA Interrupt 2 Status Event Interrupt 31 Frame Int Ratio Control Bulk Done Device Register in memory space Shared RAM Figure 11-2. Communication Channels DS785UM1 11-3 Copyright 2007 Cirrus Logic...
Page 444: Data Structures
Frame Counter as an offset into the interrupt array within the HCCA. The interrupt Endpoint Descriptors are organized into a tree structure with the head pointers being the leaf nodes. The desired polling rate of an Interrupt Endpoint is achieved by 11-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 445: Figure 11-4. Interrupt Endpoint Descriptor Structure
Endpoint Descriptors at a 16 ms poll interval, and two Endpoint Descriptors at a 32 ms poll interval. Note that in this example unused Interrupt Endpoint Placeholders are bypassed and the link is connected to the next available Endpoint in the hierarchy. DS785UM1 11-5 Copyright 2007 Cirrus Logic...
Page 446: Host Controller Driver Responsibilities
All access to the USB is scheduled by the Host Controller Driver. The Host Controller Driver allocates a portion of the available bandwidth to each periodic endpoint. If sufficient bandwidth is not available, a newly-connected periodic endpoint will be denied access to the bus. 11-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 447: List Management
The Root Hub is integrated into the HC. The internal registers of the Root Hub are exposed to the Host Controller Driver which is responsible for providing the proper hub-class protocol with the USB Driver and proper control of the Root Hub. DS785UM1 11-7 Copyright 2007 Cirrus Logic...
Page 448: Host Controller Responsibilities
Host Controller moves it to the Done Queue. Enqueuing on the Done Queue occurs by placing the most recently completed Transfer Descriptor at the head of the queue. The Done Queue is transferred periodically from the Host Controller to the Host Controller Driver via the HCCA. 11-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 449: Usb Host Controller Blocks
HCI_MBeN[3:0] (byte lane enables) and HCI_MWBstOnN (burst on) make up the width of the Data FIFO. 11.2.5.3 HCI Slave Block This block contains the OHCI operational registers, which are programmed by the Host Controller Driver (HCD). DS785UM1 11-9 Copyright 2007 Cirrus Logic...
Page 450: Hci Master Block
The Root Hub propagates Reset and Resume to downstream ports and handles port connect and disconnect. The Host Serial Interface Engine (HSIE) converts parallel to serial, serial to parallel, Non-Return to Zero Interface (NRZI) encoding/decoding and manages USB serial protocol. 11-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 451: Registers
OHCI implementation-specific. This address space is reserved for test software use. Note: Important - Before setting up any of the Host controller registers it is necessary to set the USH_EN bit (bit 28 of the PwrCnt register). DS785UM1 11-11 Copyright 2007 Cirrus Logic...
Page 452 This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this 0x10 = Compatible with OHCI 1.0. HcControl RSVD RSVD HCFS CBSR Address: 0x8002_0004 Default: 0x0000_0000 11-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 453 When disabled, HCD may modify the list. If HcControlCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list. DS785UM1 11-13 Copyright 2007 Cirrus Logic...
Page 454 POST. HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wakeup signaling of the host system is host-bus-specific and is not described in this specification. 11-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 455 The reset operation must be completed within 10 ms. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports. DS785UM1 11-15 Copyright 2007 Cirrus Logic...
Page 456 It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SchedulingOverrun in HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems. 11-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 457 UnrecoverableError. This bit is set when HC detects a system error not related to USB. HC should not proceed with any processing nor signaling before the system error has been corrected. HCD clears this bit after HC has been reset. DS785UM1 11-17 Copyright 2007 Cirrus Logic...
Page 458 WDH: WritebackDoneHead. Enable interrupt generation due to HcDoneHead Writeback. StartofFrame. Enable interrupt generation due to Start of Frame. ResumeDetected. Enable interrupt generation due to Resume Detect. UnrecoverableError. Enable interrupt generation due to Unrecoverable Error. 11-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 459 WDH: WritebackDoneHead: Disable interrupt generation due to HcDoneHead Writeback. StartofFrame: Disable interrupt generation due to Start of Frame. ResumeDetected: Disable interrupt generation due to Resume Detect. UnrecoverableError: Disable interrupt generation due to Unrecoverable Error. DS785UM1 11-19 Copyright 2007 Cirrus Logic...
Page 460 0x8002_0018 Default: 0x0000_0000 Definition: Base physical address of the Host Controller Communication Area. Bit Description: RSVD: Reserved. Unknown During Read. HCCA. Base physical address of the Host Controller Communication Area. HcPeriodCurrentED RSVD Address: 0x8002_001C 11-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 461 Physical address of the first endpoint descriptor of the control list. Bit Description: RSVD: Reserved. Unknown During Read. ControlHeadED. HC traverses the Control list starting with the HcControlHeadED pointer. The content is loaded from HCCA during the initialization of HC. DS785UM1 11-21 Copyright 2007 Cirrus Logic...
Page 462 HcControl is cleared. When set, HCD only reads the instantaneous value of this register. Initially, this is set to zero to indicate the end of the Control list. HcBulkHeadED RSVD Address: 0x8002_0028 Default: 0x0000_0000 Definition: 11-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 463 BulkListEnable of HcControl is cleared. When set, the HCD only reads the instantaneous value of this register. This is initially set to zero to indicate the end of the Bulk list. DS785UM1 11-23 Copyright 2007 Cirrus Logic...
Page 464 HCCA. It also sets the WritebackDoneHead of HcInterruptStatus. HcFmInterval FSMPS RSVD Address: 0x8002_0034 Default: 0x0000_2EDF Definition: Describes the bit time interval in a frame and the full speed maximum packet size. Bit Descriptions: 11-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 465 FrameInterval value specified in HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL state, HC re-loads the content with the FrameInterval of HcFmInterval and uses the updated value from the next SOF. DS785UM1 11-25 Copyright 2007 Cirrus Logic...
Page 466 FrameNumber at each frame boundary and sent a SOF but before HC reads the first ED in that Frame. After writing to HCCA, HC will set the StartofFrame in HcInterruptStatus. HcPeriodicStart RSVD RSVD Address: 11-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 467 FrameRemaining field prior to initiating a Low Speed transaction. The transaction is started only if FrameRemaining >= this field. The value is calculated by HCD with the consideration of transmission and setup overhead. DS785UM1 11-27 Copyright 2007 Cirrus Logic...
Page 468 If the PortPowerControlMask bit is set, the port responds only to port power commands (Set/ClearPortPower). If the port mask is cleared, the port is controlled only by the global power switch (Set/ClearGlobalPower). 11-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 469 Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as P[7:0] * 2 ms. 0x05 = 10 ms HcRhDescriptorB RSVD PPCM RSVD Address: 0x8002_004C DS785UM1 11-29 Copyright 2007 Cirrus Logic...
Page 470 1: Ganged-power mask on Port #1 bit 2: Ganged-power mask on Port #2 bit 3: Ganged-power mask on Port #3 HcRhStatus CRWE RSVD CCIC LPSC DRWE RSVD Address: 0x8002_0050 Default: 0x0000_0000 Definition: Root hub status. Bit Descriptions: 11-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 471 OCI field of this register. The HCD clears this bit by writing a “1”. Writing a “0” has no effect. CRWE: (WRITE) ClearRemoteWakeupEnable. Writing a '1' clears DeviceRemoveWakeupEnable. Writing a '0' has no effect. DS785UM1 11-31 Copyright 2007 Cirrus Logic...
Page 472 (WRITE) ClearPortEnable: The HCD writes a “1” to this bit to clear the PortEnableStatus bit. Writing a “0” has no effect. The CurrentConnectStatus is not affected by any write. Note: This bit is always read “1” when the attached device is nonremovable (DeviceRemoveable.NDP). 11-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 473 PortSuspendStatus bit by writing a “1” to this bit. Writing a “0” has no effect. If CurrentConnectStatus is cleared, this write does not set PortSuspendStatus; instead it sets ConnectStatusChange. This informs the driver that it attempted to suspend a disconnected port. DS785UM1 11-33 Copyright 2007 Cirrus Logic...
Page 474 Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ClearGlobalPower commands are enabled. When port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and PortResetStatus should be reset. 0 = port power is off 1 = port power is on 11-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 475 The HCD writes a “1” to clear this bit. Writing a “0” has no effect. This bit is also cleared when ResetStatusChange is set. 0 = resume is not completed 1 = resume completed DS785UM1 11-35 Copyright 2007 Cirrus Logic...
Page 476 1 ms frame duration used internally. It should be usually set to “0”. Setting it to “1” will cause the internal counter count to be a partial full count. 11-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 477 RWU: Host controller remote wakeup. Software action when this bit is asserted is implementation specific. It is a status bit reporting a transition of internal state. DS785UM1 11-37 Copyright 2007 Cirrus Logic...
Page 478 Universal Serial Bus Host Controller EP93xx User’s Guide 11-38 DS785UM1 Copyright 2007 Cirrus Logic...
Page 479: Chapter 12. Static Memory Controller
Note: There are only two external DMA interfaces total on the EP93xx device to control data flow • Non-burst read and write accesses • Page Mode (burst-of-four) read and write accesses • PCMCIA interfacing (EP9315 processor only) DS785UM1 12-1 Copyright 2007 Cirrus Logic...
Page 480: Static Memory Controller Operation
HCLK cycles. • When both N and are used, the SMC holds its bus state for N HCLK cycles or WAITn until WAITn is sampled as being de-asserted, whichever occurs last. 12-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 481: Figure 12-1. 32-Bit Read, 32-Bit Memory, 0 Wait Cycles, Rble = 1, Waitn Inactive
Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive AD[x] Data Write DA[x] nCSx WRn and nDMQ[3:0] HCLK Figure 12-2. 32-bit Write, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive DS785UM1 12-3 Copyright 2007 Cirrus Logic...
Page 482: Figure 12-3. 16-Bit Read, 16-Bit Memory, Rble = 1, Waitn Active
Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Active AD[x] Data Write DA[x] nCSx WRn and nDMQ[1:0] Delay due to WAITn synchronization WAITn HCLK Figure 12-4. 16-bit Write, 16-bit Memory, RBLE = 1, WAITn Active 12-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 483: Pcmcia Interface (Ep9315 Processor Only)
Undefined 0x4400_0000 - 0x47FF_FFFF Attribute 0x4800_0000 - 0x4BFF_FFFF Memory 0x4C00_0000 - 0x4FFF_FFFF Table 12-2. PCMCIA Pin Usage Alternate Use If Pin Name PCMCIA Signal Name Note: No Card MCRDn nPOE MCWRn nPWE IORDn nPIORD DS785UM1 12-5 Copyright 2007 Cirrus Logic...
Page 484 IO space registers accordingly. External logic, as shown in Figure 12-5, is required to connect some PCMCIA card signals to the processor. Other PCMCIA card signals, also shown in Figure 12-5, connect directly to the processor. 12-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 485: Figure 12-5. Single Pc Card Interface
Pins AD[7:0] PC_A[7..0] Address Buffer MCADENn PC_A[25:8] AD[25:8] MCWRn nPWE MCRDn nPOE MCWAIT nWAIT MCEHn nPC_CE2 MCELn nPC_CE1 IORDn nPIORD IOWRn nPIOWR MCREGn nPREG MCRESETn RESET_1 READY PC_RDY Figure 12-5. Single PC Card Interface DS785UM1 12-7 Copyright 2007 Cirrus Logic...
Page 486: Pc Card Memory-Mode Enable Signals
Table 12-6 Table 12-7, bit 1 and bit 0 of the address each show a value of Note: In 0b1, 0b0, or 0bx. [25:2] refers to bit positions of the address, not address values. 12-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 487: Table 12-6. Accesses To 8-Bit Attribute / Common / Io Memory
Lower AD[25:2],x,x [15:8] [7:0] Invalid [7:0] Half-Word Upper AD[25:2],x,x [31:24] [23:16] Invalid [23:16] Half-Word Byte 0 AD[25:2],x,0 [7:0] [7:0] Byte 1 AD[25:2],0,1 [15:8] Invalid Byte 2 AD[25:2],x,0 [23:16] [23:16] Byte 3 AD[25:2],x,1 [31:24] Invalid DS785UM1 12-9 Copyright 2007 Cirrus Logic...
Page 488: Registers
SMCBCR3: 0x8008_000C - Read/Write SMCBCR6: 0x8008_0018 - Read/Write SMCBCR7: 0x8008_001C - Read/Write Default: 0x2000_FBE0 Definition: SMC Bank Configuration registers These registers are used to specify the characteristics and timing for each of the memory banks, respectively. 12-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 489 The value in this field specifies the ‘number of HCLK cycles, minus 1’ that are inserted as wait cycles into the timing for each of the 2nd, 3rd, and 4th accesses of Read or Write burst-of-four accesses. DS785UM1 12-11 Copyright 2007 Cirrus Logic...
Page 490 This takes place following a power-on reset, but only if the input values on these pins are: ASDO = ‘0’, Boot[1:0] = ‘00’, EEDAT = ‘1’. and EECLK = ‘0’. 12-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 491: Pcmcia Configuration Registers (Ep9315 Processor Only)
Attribute Space Access time - Read/Write The value written to this field specifies the minimum ‘number of HCLK cycles, minus 1’ that the data strobe, MCDAENn is asserted during a Read or Write access. DS785UM1 12-13 Copyright 2007 Cirrus Logic...
Page 492 Common Space Width - Read/Write The value written to this bit specifies the bus-width of the Common space: 0 - 8-bit wide Common space 1 - 16-bit wide Common space Common Space Access time - Read/Write 12-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 493 Address: 0x8008_0028 - Read/Write Default: 0x0000_0000 Definition: PC Card IO register Bit Descriptions: RSVD: Reserved - Unknown During Read IO Space Width - Read/Write The value written to this bit specifies the bus-width of the IO space: DS785UM1 12-15 Copyright 2007 Cirrus Logic...
Page 494 PI = 0x25, the Setup time is 37 + 1 = 38 cycles of HCLK. PCMCIACtrl RSVD RSVD RSVD PCRST RSVD PCEN Address: 0x8008_0040 - Read/Write Default: 0x0000_0000 Definition: PC Card Control register Bit Descriptions: RSVD: Reserved - Unknown During Read 12-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 495 Writing a ‘1’ to this bit enables the MCWAIT input pin to be asserted by the card to insert wait cycles into the access timing. Writing a ‘0’ to this bit disables the MCWAIT input pin from being asserted by the card. DS785UM1 12-17 Copyright 2007 Cirrus Logic...
Page 496 Static Memory Controller EP93xx User’s Guide 12-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 497: Chapter 13. Sdram, Syncrom, And Syncflash Controller
SDRAMDevCfg[3:0], is used for booting. For a Synchronous ROM device, the configuration sequence writes RAS = 0x2 and CAS = 0x5 to the SDRAMDevCfg[3:0] register and writes RAS = 0x2, CAS = 0x5, and either Burst DS785UM1 13-1 Copyright 2007 Cirrus Logic...
Page 498: Table 13-1. Boot Device Selection
Burst Length = 0x4 (32-bit wide memory bus) or Burst Length = 0x8 (16-bit wide memory bus). 4. Three SDCLK cycles after the Mode register is written with the appropriate default value, the memory portion of the synchronous memory device is ready for power-up with all of 13-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 499: Address Pin Usage
Because some address bits are not used, the address map of the synchronous memory appears to be non- continuous. The SROMLL should be used when possible to reduce the number of “holes” in DS785UM1 13-3 Copyright 2007 Cirrus Logic...
Page 500: Sdram Initialization
(refer to the SDRAM device’s data sheet to ensure compatibility). Table 13-4. General SDRAM Initialization Sequence Step Action Reason To allow SDRAM power and clocks to Wait 100 μ s stabilize 13-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 501 "SDRAMDevCfg[3:0]" register. Write other fields in the "SDRAMDevCfg[3:0]"register as appropriate for the given SDRAM usage. Write Initialize = ‘0’, MRS = ‘0’, and LCR = ‘0’ to the To start normal operation "GlConfig" register. DS785UM1 13-5 Copyright 2007 Cirrus Logic...
Page 502: Programming Mode Register: Sdram Or Syncrom Device
Note: If using an external bus that is 16 bits wide then the address mapping must be shifted as indicated by Table 13-3 on page 13-4. Note: For SDRAM, AD[2:0] specify burst length. For SROM, AD[1:0] specify burst length. 13-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 503: Table 13-6. Sync Memory Cas
• SDRAM default READ Address: 0xH000_C800 — sets WBM=0, TM=0, CAS=3, Sequential, BL=4 • SFLASH default READ Address: 0xH008_C800 — sets WBM=1, TM=0, CAS=3, Sequential, BL=4 • SROM default READ Address: 0xH001_8400 — sets RAS=2, CAS=5, Sequential, BL=4 DS785UM1 13-7 Copyright 2007 Cirrus Logic...
Page 504: Sdram Self Refresh
Then, write LCR = ‘1’ to the GlConfig register. Doing so causes the value of a subsequent read address to be used as the data value that is written 13-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 505: External Synchronous Memory System
The latched value of ASDO determines how SDCSn3 is mapped into synchronous memory space. If the latched value of ASDO=1 then SDCSn3 is mapped to 0x0000_0000 otherwise it is mapped to 0xF000_0000. Table 13-9. Chip Select Decoding Boot Option Chip select (ASDO) nSDCS3 DS785UM1 13-9 Copyright 2007 Cirrus Logic...
Page 506: Address/Data/Control Required By Memory System
For each 16-bit Write, DQM[1:0] = ‘00’ and DQM[3:2] are not used. Table 13-10 shows a memory addressing example for a 256 Mbit synchronous memory device with 13-row x 9-column x 2-bank addressing attached to a 16-bit memory bus. Note 13-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 507: Table 13-10. Memory Addressing Example
Note that in the “Continuous Address Range Per Segment” column, the value N can be 0x0, 0xC, 0xD, 0xE or 0xF as shown in Table 13-12. DS785UM1 13-11 Copyright 2007 Cirrus Logic...
Page 508: Table 13-11. Ep93Xx Sdram Address Ranges (16-Bit Wide Data Systems)
Table 13-11. EP93xx SDRAM Address Ranges (16-Bit Wide Data Systems) SROMLL = 0 SROMLL = 1 Device Total Size, Address Organization Bank Type Matrix Continuous Address Size of Continuous Address Size of Size System Range (see Note) Segment Range (see Note) Segment 0xN000_0000 - 0xN01F_FFFF 64 Mbit (16-bit...
Page 509 Table 13-11. EP93xx SDRAM Address Ranges (16-Bit Wide Data Systems) (Continued) SROMLL = 0 SROMLL = 1 Device Total Size, Address Organization Bank Type Matrix Continuous Address Size of Continuous Address Size of Size System Range (see Note) Segment Range (see Note) Segment 0xN300_0000 - 0xN33F_FFFF 0xN400_0000 - 0xN43F_FFFF...
Page 510 Table 13-11. EP93xx SDRAM Address Ranges (16-Bit Wide Data Systems) (Continued) SROMLL = 0 SROMLL = 1 Device Total Size, Address Organization Bank Type Matrix Continuous Address Size of Continuous Address Size of Size System Range (see Note) Segment Range (see Note) Segment 64 Mbit (32-bit 12 x 8 x 2...
Page 511 Table 13-11. EP93xx SDRAM Address Ranges (16-Bit Wide Data Systems) (Continued) SROMLL = 0 SROMLL = 1 Device Total Size, Address Organization Bank Type Matrix Continuous Address Size of Continuous Address Size of Size System Range (see Note) Segment Range (see Note) Segment 256 Mbit (32- 13 x 8 x 4...
Page 512 Table 13-11. EP93xx SDRAM Address Ranges (16-Bit Wide Data Systems) (Continued) SROMLL = 0 SROMLL = 1 Device Total Size, Address Organization Bank Type Matrix Continuous Address Size of Continuous Address Size of Size System Range (see Note) Segment Range (see Note) Segment 0xN300_0000 - 0xN37F_FFFF 0xN400_0000 - 0xN47F_FFFF...
Page 513: Registers
Refresh Timer 0x8006_000C "BootSts" Boot Configuration Pins Status "SDRAMDevCfg[3:0]" (See Below) 0x8006_0010 SDRAMDevCfg[3:0] Synchronous Device Configuration 0 0x8006_0014 SDRAMDevCfg[3:0] Synchronous Device Configuration 1 0x8006_0018 SDRAMDevCfg[3:0] Synchronous Device Configuration 2 0x8006_001C SDRAMDevCfg[3:0] Synchronous Device Configuration 3 DS785UM1 13-17 Copyright 2007 Cirrus Logic...
Page 514 Writing a value to this bit specifies if the HCLK output on the SDCLK pin is free-running or gated off: 0 - SDCLK is free-running 1 - SDCLK is gated off only when there is no current access to any synchronous memory device 13-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 515 ‘1’, subsequent Read accesses to the synchronous device cause commands on the AD[13:0] pins to be written to the Mode register. 0 - See Table 13-14 1 - See Table 13-14 Initialize: Initialize bit - Read/Write DS785UM1 13-19 Copyright 2007 Cirrus Logic...
Page 516: Table 13-14. Synchronous Memory Command Encoding
Enable access to Synchronous Memory device mode register Issue command to Synchronous FLASH Memory devices UNDEFINED. Do not use. UNDEFINED. Do not use. UNDEFINED. Do not use. Normal operation RefrshTimr RSVD Refcnt Address: 0x8006_0008 - Read/Write Default: 0x0000_0080 13-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 517 Bit Descriptions: RSVD: Reserved - Unknown During Read ASDO: Latched ASDO pin value - Read Only Boot Media: 1 - SyncROM or SyncFLASH 0 - Asynchronous ROM Width: Boot memory bus Width - Read Only DS785UM1 13-21 Copyright 2007 Cirrus Logic...
Page 518 RSVD RasToCas CasLat Precharge RSVD SFConfig SROMLL SROM512 Bank External RSVD Addr PAGE Count Width Address: SDRAMDevCfg0: 0x8006_0010 - Read/Write SDRAMDevCfg1: 0x8006_0014 - Read/Write SDRAMDevCfg2: 0x8006_0018 - Read/Write SDRAMDevCfg3: 0x8006_001C - Read/Write Default: 0x0122_0008 13-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 519 When performing a Write access, the Synchronous Memory controller automatically adds one SDCLK cycle to the RasToCas value. When performing a Read access, the Synchronous Memory controller uses the RasToCas value as it is. WBM: Write Burst Mode - Read/Write DS785UM1 13-23 Copyright 2007 Cirrus Logic...
Page 520 SyncFLASH device: 0 - Normal operation 1 - Read SyncFLASH Configuration register The AutoPrecharge bit must be ‘0’ before the SFConfigAddr bit is written to ‘1’. 2KPAGE: Synchronous memory 2K byte Page - Read/Write 13-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 521 Bank Count - Read/Write The value written to this bit specifies the number of banks that are inside an SDRAM device: 1 - Four banks 0 - Two banks External Bus Width:External Bus Width - Read/Write DS785UM1 13-25 Copyright 2007 Cirrus Logic...
Page 522 SDRAM, SyncROM, and SyncFLASH Controller EP93xx User’s Guide The value written to this bit specifies the width of the memory bus: 0 - Width is 32-bits 1 - Width is 16-bits 13-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 523: Chapter 14. Uart1 With Hdlc And Modem Control Signals
If a framing, parity or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten. DS785UM1 14-1 Copyright 2007 Cirrus Logic...
Page 524: Uart Functional Description
Note that configuration of the DMA channels in the DMA engine is also required for DMA operation with the UART. 14.2.1.3 Register Block The register block stores data written or to be read across the AMBA APB interface. 14-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 525: Figure 14-1. Uart Block Diagram
UART1 With HDLC and Modem Control Signals EP93xx User’s Guide UARTTXD AMBA Interface AMBA Register Block Interface UARTRXD Figure 14-1. UART Block Diagram DS785UM1 14-3 Copyright 2007 Cirrus Logic...
Page 526: Baud Rate Generator
Separate receive and transmit FIFO status signals indicate to the DMA interface when there is room in the transmit FIFO for more data and when there is data in the receive FIFO. 14-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 527: Synchronizing Registers And Logic
Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word has been received, the data is stored in the receive FIFO, with any error bits associated with that word (see Table 14-1). DS785UM1 14-5 Copyright 2007 Cirrus Logic...
Page 528: Error Bits
Data transmitted on UARTTXD output will be received on the UARTRXD input. 14.2.2.4 UART Character Frame The UART character frame is shown in Figure 14-2: Figure 14-2. UART Character Frame Figure 14-3. UART Character Frame 14-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 529: Interrupts
• If the FIFOs are enabled and the transmit FIFO is at least half empty (it has space for eight or more words), then the transmit interrupt is asserted HIGH. It is cleared by filling the transmit FIFO to more than half full. DS785UM1 14-7 Copyright 2007 Cirrus Logic...
Page 530: Uartrtintr
TXE and/or RXE bit. This insures that no bytes are sent by the UART transmitter without proper HDLC framing, and that no bytes are received via the UART receiver without proper HDLC decoding. In HDLC mode, the UART should be configured to use 8-bit characters and no parity bit. 14-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 531: Overview Of Hdlc Modes
14.4.2 Selecting HDLC Modes By default, HDLC is NRZ-encoded. Set bit UART1HDLCCtrl.TXENC to force Manchester encoding in the transmitter, and set bit UART1HDLCCtrl.RXENC to make the receiver expect Manchester encoding. DS785UM1 14-9 Copyright 2007 Cirrus Logic...
Page 532: Table 14-2. Legal Hdlc Mode Configurations
Asynchronous NRZ Asynchronous NRZ Synchronous NRZ Synchronous NRZ Synchronous NRZ Manchester Manchester Synchronous NRZ Manchester Manchester Synchronous NRZ External clock Manchester External clock External clock Synchronous NRZ External clock Manchester Internal clock Synchronous NRZ 14-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 533: Hdlc Transmit
Processed bytes are placed in the receive FIFO. When programmed to receive a Manchester encoded bit stream, UART1HDLCSts.PLLCS indicates whether the DPLL in the receiver has locked on to the carrier. DS785UM1 14-11 Copyright 2007 Cirrus Logic...
Page 534: Crcs
UART1HDLCAddMtchVal specifies an address to match and the corresponding half- word in UART1HDLCAddMask specifies which bits of each address to match. Hence, up to four different one-byte addresses and two different two-byte addresses may be specified. An 14-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 535: Aborts
Finally, if the packet is too short, that is, there are not enough received bytes to hold the specified number of address and CRC bytes, the entire packet will appear in the receive FIFO. In all cases, the packet is illegal and will be ignored by the CPU. DS785UM1 14-13 Copyright 2007 Cirrus Logic...
Page 536: Dma
The simplest way to due this is separate the two writes by 55 NOPs. 14.5 UART1 Package Dependency UART1 uses package pins RXD0, TXD0, CTSn, DSRn, DTRn, RTSn, EGPIO[3], and EGPIO[0], which are described in Table 14-4. 14-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 537: Clocking Requirements
The frequency of UARTCLK must also be within the required error limits for all baud rates to be used. To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less than or equal to four times the frequency of PCLK: ≤ × UARTCLK PCLK DS785UM1 14-15 Copyright 2007 Cirrus Logic...
Page 538: Bus Bandwidth Requirements
65,829 characters per second. Using the DMA interface would result in 16,457 AHB accesses per second, while using the APB to access the UART leads to 65,829 bus accesses per second. 14-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 539: Registers
(the bottom word of the receive FIFO). The received data byte is read by performing reads from the UART1Data register while the corresponding status information can be read by a successive read of the UART1RXSts register. DS785UM1 14-17 Copyright 2007 Cirrus Logic...
Page 540 UART1LinCtrlHigh (bit 2). This bit is cleared to 0 by a write to UART1RXSts. In FIFO mode, this error is associated with the character at the top of the FIFO. 14-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 541 • UART1LinCtrlLow write (or UART1LinCtrlMid write) and UART1LinCtrlHigh write. Bit Descriptions: RSVD: Reserved. Unknown During Read. WLEN: Number of bits per frame: 11 = 8 bits 10 = 7 bits 01 = 6 bits 00 = 5 bits DS785UM1 14-19 Copyright 2007 Cirrus Logic...
Page 542 The transmit FIFO contents remain unaffected during a break condition. 0 - For normal use, this bit must be cleared. UART1LinCtrlMid RSVD RSVD Address: 0x808C_000C - Read/Write Default: 0x0000_0000 14-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 543 BAUDDIV = (F / 16 * Baud rate)) – 1 UARTCLK where F is the UART reference clock frequency. A UARTCLK baud rate divisor of zero is not allowed and will result in no data transfer. DS785UM1 14-21 Copyright 2007 Cirrus Logic...
Page 544 UARTE: UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for UART signals. UART1Flag RSVD RSVD TXFE RXFF TXFF RXFE BUSY 14-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 545 That is, the bit is 1 when the modem status input is DSR: Data Set Ready status. This bit is the complement of the UART data set ready (nUARTDSR) modem status input. That is, the bit is 1 when the modem status input is 0. DS785UM1 14-23 Copyright 2007 Cirrus Logic...
Page 546 0 - The receive FIFO is empty. MIS: Modem Interrupt Status. This bit is set to 1 if the UARTMSINTR modem status interrupt is asserted. This bit is cleared by writing any value to this register. 14-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 547 DMA interface to the transmit FIFO. RXDMAE: RX DMA interface enable. Setting to 1 enables the private DMA interface to the receive FIFO. Modem Register Descriptions UART1ModemCtrl RSVD RSVD LOOP OUT2 OUT1 Address: 0x808C_0100 - Read/Write DS785UM1 14-25 Copyright 2007 Cirrus Logic...
Page 548 1 - RTSn pin low 0 - RTSn pin high DTR: DTR output signal: 1 - DTRn pin low 0 - DTRn pin high UART1ModemSts RSVD RSVD DDCD TERI DDSR DCTS Address: 0x808C_0104 - Read Only Default: 0x0000_0000 14-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 549 TXENC RXENC SYNC TFCEN TABEN RFCEN RILEN RFLEN RTOEN FLAG CRCN CRCApd IDLE IDLSpc CRCZ CRCE CRCS Address: 0x808C_020C - Read/Write Default: 0x0000_0000 Definition: HDLC Control Register Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 14-27 Copyright 2007 Cirrus Logic...
Page 550 1 - TAB interrupt will occur whenever TAB bit is set. RFCEN: Receive Frame Complete Interrupt Enable. 0 - RFC interrupt will not occur. 1 - RFC interrupt will occur whenever RAB bit or EOF bit is set. 14-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 551 11 - Undefined, no matching IDLSpc: Idle in space 0 - TX idle in mark (normal) 1 - TX idle in space RX will receive Manchester encoded data whether it idles in mark or space. DS785UM1 14-29 Copyright 2007 Cirrus Logic...
Page 552 1 - CRC-32: x + x + 1 If inverted (see CRCN bit) the CRC-16 check value is 0x1D0F and the CRC-32 check value is 0xC704_DD7B. Otherwise the check value is zero. UART1HDLCAddMtchVal Address: 0x808C_0210 - Read/Write 14-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 553 Address mask value. Supports 8-bit and 16-bit address masking. If UART1HDLCCtrl.AME[1:0] is 00b or 11b, this register is not used. UART1HDLCRXInfoBuf RSVD BPLLE RSVD RSVD BFRE BROR BCRE BRAB Address: 0x808C_0218 - Read Only Default: 0x0000_0000 DS785UM1 14-31 Copyright 2007 Cirrus Logic...
Page 554 CRC value contained in the last frame. BRAB: Buffered Receiver Abort. 0 - No abort occurred in the last frame. 1 - The last frame was aborted. UART1HDLCSts RSVD PLLE PLLCC LNKIDL RSVD 14-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 555 The rest of the incoming frame is dropped. EOF is also set. Note: This bit reflects the status associated with the last character read from the RX FIFO. It changes with reads from the RX FIFO. DS785UM1 14-33 Copyright 2007 Cirrus Logic...
Page 556 Set to “1” when the last data byte for the frame is read from the RX FIFO (this also triggers an update of the UART1HDLCRXInfoBuf). Cleared by writing to a “1” to this bit. 14-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 557 This bit is a copy of the TIS bit in the UART interrupt identification register. 0 - TX FIFO is full or TX disabled. 1 - TX FIFO not full and TX enabled. May generate an interrupt and signal a DMA service request. DS785UM1 14-35 Copyright 2007 Cirrus Logic...
Page 558 UART1 With HDLC and Modem Control Signals EP93xx User’s Guide 14-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 559: Introduction
The IrDA SIR physical layer specifies a minimum 10 ms delay between transmission and reception. 15.2.1 IrDA SIR Encoder/decoder Functional Description The IrDA SIR Encoder/decoder comprises: • IrDA SIR transmit encoder • IrDA SIR receive decoder This is shown in Figure 15-1: DS785UM1 15-1 Copyright 2007 Cirrus Logic...
Page 560: Irda Sir Transmit Encoder
NRZ serial bit stream to the UART received data input. The decoder input is normally HIGH (marking state) in the idle state (the transmit encoder output has the opposite polarity to the decoder input). 15-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 561: Irda Sir Operation
The low-power divisor value is calculated as: Low-power divisor = (FUARTCLK / FirLPBaud16) -1 where FirLPBaud16 is nominally 1.8432 MHz. The divisor must be chosen so that 1.42 MHz < IrLPBaud16 < 2.12 MHz. DS785UM1 15-3 Copyright 2007 Cirrus Logic...
Page 562: System/Diagnostic Loopback Testing
Note: UART2TMR is the only occasion that a test register needs to be accessed during normal operation. 15.2.3 IrDA Data Modulation The effect of IrDA 3/16 data modulation can be seen in Figure 15-2. Figure 15-2. IrDA Data Modulation (3/16) 15-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 563: Enabling Infrared (Ir) Modes
The frequency of UARTCLK must also be within the required error limits for all baud rates to be used. To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less than or equal to four times the frequency of PCLK: DS785UM1 15-5 Copyright 2007 Cirrus Logic...
Page 564: Bus Bandwidth Requirements
65829 APB characters per second. Using the DMA interface would result in 16457 AHB accesses per second, while using the APB to access the UART leads to 65829 bus accesses per second. 15-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 565: Registers
3-bit status (break, frame and parity) is pushed onto the 11-bit wide receive FIFO • if the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). DS785UM1 15-7 Copyright 2007 Cirrus Logic...
Page 566 UART2LinCtrlHigh (bit 2). This bit is cleared to 0 by a write to UART2RXSts. In FIFO mode, this error is associated with the character at the top of the FIFO. 15-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 567 UART2LinCtrlLow write (or UART2LinCtrlMid write) and UART2LinCtrlHigh write. Bit Descriptions: RSVD: Reserved. Unknown During Read. WLEN: Number of bits per frame: 11 = 8 bits 10 = 7 bits 01 = 6 bits 00 = 5 bits DS785UM1 15-9 Copyright 2007 Cirrus Logic...
Page 568 The transmit FIFO contents remain unaffected during a break condition. 0 - For normal use, this bit must be cleared. UART2LinCtrlMid RSVD RSVD Address: 0x808D_000C - Read/Write Default: 0x0000_0000 15-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 569 Baud rate divisor BAUDDIV = (F / (16 * Baud UARTCLK rate)) –1 where F is the UART reference clock frequency. A UARTCLK baud rate divisor of zero is not allowed and will result in no data transfer. DS785UM1 15-11 Copyright 2007 Cirrus Logic...
Page 570 RIE: Receive Interrupt Enable. If this bit is set to “1”, the receive interrupt is enabled. MSIE: Modem Status Interrupt Enable. If this bit is set to “1”, the modem status interrupt is enabled. 15-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 571 FEN bit in the UART2LinCtrlHigh register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. DS785UM1 15-13 Copyright 2007 Cirrus Logic...
Page 572 Clear To Send status. This bit is the complement of the UART clear to send (nUARTCTS) modem status input. That is, the bit is “1” when the modem status input is 0. UART2IntIDIntClr RSVD RSVD RTIS Address: 0x808D_001C 15-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 573 IrLPBaud16 signal by dividing down of UARTCLK. All the bits are cleared to 0 when reset. Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 15-15 Copyright 2007 Cirrus Logic...
Page 574 TXDMAE: TX DMA interface enable. Setting to “1” enables the private DMA interface to the transmit FIFO. RXDMAE: RX DMA interface enable. Setting to “1” enables the private DMA interface to the receive FIFO. 15-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 575 UART2Ctrl bit 7, Loop Back Enable been set to “1”. Clearing this bit to 0 disabled the receive logic when the SIR is transmitting (normal operation). This bit defaults to 0 for normal (half-duplex) operation. DS785UM1 15-17 Copyright 2007 Cirrus Logic...
Page 577: Introduction
Table 16-1. UART3 Pin Functionality Description RXD2 UART2 input pin TXD2 UART2 output pin EGPIO[3] HDLC clock or TENn The use of EGPIO[3] is determined by several bits in Syscon register DeviceCfg. See Table 16-2 for details. DS785UM1 16-1 Copyright 2007 Cirrus Logic...
Page 578: Clocking Requirements
UART. Accessing the UART through the DMA interface requires one access per 32-bits, implying only 20,945 / 4 = 5,236 AHB accesses per second. Accessing the UART through the APB requires two accesses per byte, implying 20,945 APB buss accesses. 16-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 579: Registers
(if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: • if the FIFOs are enabled, the data byte is extracted, and DS785UM1 16-3 Copyright 2007 Cirrus Logic...
Page 580 The FIFO contents remain valid since no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The data must be read in order to empty the FIFO. 16-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 581 UART3LinCtrlMid or UARTBLCR_L, a UART3LinCtrlHigh write must always be performed at the end. To update the three registers there are two possible sequences: • UART3LinCtrlLow write, UART3LinCtrlMid write and UART3LinCtrlHigh write DS785UM1 16-5 Copyright 2007 Cirrus Logic...
Page 582 This bit must be asserted for at least one complete frame transmission time in order to generate a break condition. The transmit FIFO contents remain unaffected during a break condition. 0 - For normal use, this bit must be cleared. 16-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 583 Baud Rate Divisor bits [15:8]. Most significant byte of baud rate divisor. These bits are cleared to 0 on reset. UART3LinCtrlLow RSVD RSVD Address: 0x808E_0010 - Read/Write Default: 0x0000_0000 Definition: UART3 Line Control Register Low. Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 16-7 Copyright 2007 Cirrus Logic...
Page 584 Modem Status Interrupt Enable. If this bit is set to 1, the modem status interrupt is enabled. UARTE: UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for UART signals. 16-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 585 FEN bit in the UART3LinCtrlHigh register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. DS785UM1 16-9 Copyright 2007 Cirrus Logic...
Page 586 RTIS: Receive Timeout Interrupt Status. This bit is set to 1 if the receive timeout interrupt is asserted. This bit is cleared when the receive FIFO is empty or the receive line goes active. 16-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 587 Definition: UART3 IrDA Low Power Divisor Register. This register is present in UART3 but is not supported. Bit Descriptions: RSVD: Reserved. Unknown During Read. UART3DMACtrl RSVD RSVD DMAERR TXDMAE RXDMAE Address: 0x808E_0028 - Read/Write DS785UM1 16-11 Copyright 2007 Cirrus Logic...
Page 588 TENn is low whenever the UART has transmit data to send. 0 = TENn is controlled by the OUT1 bit. OUT1: OUT1 function. When OUT2 = “0”, then TENn = OUT1. Otherwise OUT1 is ignored. 16-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 589 This bit has no effect unless RXENC is clear and synchronous HDLC is enabled. TXENC: Transmit Encoding method. 1 - Use Manchester bit encoding. 0 - Use NRZ bit encoding. This bit has no effect unless synchronous HDLC is enabled DS785UM1 16-13 Copyright 2007 Cirrus Logic...
Page 590 Note that HDLC RX does not count flags; only one is necessary (or three in Manchester mode). CRCN: CRC polarity control. 0 - CRC transmitted not-inverted. 1 - CRC transmitted inverted. 16-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 591 1 - HDLC TX automatically generates and sends a CRC at the end of a packet, and HDLC RX expects a CRC at the end of a packet. CRCS: CRC size. 0 - CRC-16: x 1 - CRC-32: x + x + 1 DS785UM1 16-15 Copyright 2007 Cirrus Logic...
Page 592 AMSK Address: 0x808E_0214 - Read/Write Default: 0x0000_0000 Definition: HDLC Address Mask. Bit Descriptions: AMSK: Address mask value. Supports 8-bit and 16-bit address masking. If UART3HDLCCtrl.AME is “00” or “11”, this register is not used. 16-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 593 1 - The CRC calculated on the incoming data did not match the CRC value contained in the last frame. BRAB: Buffered Receiver Abort. 0 - No abort occurred in the last frame. 1 - The last frame was aborted. DS785UM1 16-17 Copyright 2007 Cirrus Logic...
Page 594 1 - TX is currently sending a frame (address, control, data, CRC or start/stop flag). RIF: Receiver In Frame. (Read Only) 0 - RX is idle, disabled or receiving start flags 1 - RX is receiving a frame. 16-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 595 This bit is a copy of the RIS bit in the UART interrupt identification register. 0 - RX FIFO is empty or RX is disabled. 1 - RX FIFO not empty and RX enabled. May generate an interrupt and signal a DMA service request. DS785UM1 16-19 Copyright 2007 Cirrus Logic...
Page 596 This bit is a copy of the TIS bit in the UART interrupt identification register. 0 - TX FIFO is full or TX disabled. 1 - TX FIFO not full and TX enabled. May generate an interrupt and signal a DMA service request. 16-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 597: Introduction
• Medium Infrared - MIR - This interface is independent of a UART. Transmission/reception rates can be 0.576 or 1.152 Mbit/sec. • Fast Infrared - FIR - This interface is independent of a UART. Transmission/reception rates can be 4 Mbit/sec. DS785UM1 17-1 Copyright 2007 Cirrus Logic...
Page 598: Shared Irda Interface Feature
APB via the Infrared interface. 17.3.2 Functional Description This section gives a programmer's guide to operating the IrDA interface. It includes detail on the general configuration and the transmit and receive processes. 17-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 599: General Configuration
The DMA route is usually provided to overcome any large interrupt response times that may exist in the SoC where the Infrared module is going to be used. These large interrupt response times can make programmed I/O an impractical method for transferring large Ir data packets. DS785UM1 17-3 Copyright 2007 Cirrus Logic...
Page 600 12.Send out the data - If DMA is being used, everything is now enabled for the transmission process to begin. If PIO or IRQ is being used, data should be written to the IrData register. 17-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 601: Receiving Data
The following settings are required: Address Matching To use Address Match filtering, set the local 8 bit address in the Address Match Value Register and set the Address Match Enable bit in the IrCon register. DS785UM1 17-5 Copyright 2007 Cirrus Logic...
Page 602 If the CRC for the received data does not match the CRC value contained in the incoming data stream this condition will occur. Frame Error (FIR only) This indicates that a framing error has been detected. 17-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 603: Special Conditions
17.3.2.4.4 Loopback Mode For test purposes, data will be looped back – internally – from the output of the transmit serial shifter into the input of the receive serial shifter when IrEnable.LBM is set. DS785UM1 17-7 Copyright 2007 Cirrus Logic...
Page 604: Control Information Buffering
For both 0.576 and 1.152 Mbps data rates, the optical pulse duration is normally 1/4 of a bit duration. For example, if the data frame (in the order of transmission) is 11010010b, then Figure 17-1 represents the signal that is actually transmitted. 17-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 605: Frame Format
8 Bits Any multiple 8 Bits 8 Bits 8 Bits 16 Bits 8 Bits (optional) of 8 Bits Start Flag Start Flag Stop Flag Address Control Data CRC-CCITT 0111 1110 0111 1110 0111 1110 DS785UM1 17-9 Copyright 2007 Cirrus Logic...
Page 606 Note that the CRC is transmitted and received starting with its MSB and ending with its LSB. The CRC uses the four term polynomial: CRC(x) = (x + 1) 17-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 607: Functional Description
If the values do not match, the receive logic does not store any data in the DS785UM1 17-11 Copyright 2007 Cirrus Logic...
Page 608 If the user disables the receiver during operation, reception of the current data byte is stopped immediately, the serial shifter and receive buffer are cleared and all clocks used by the receive logic are automatically shut off to conserve power. 17-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 609: Transmit Operation
Infrared Data Association (IrDA) compliant LED transceivers. The FIR supports the 4.0 Mbps IrDA standard, using four pulse position modulation (4 PPM) and a specialized serial packet protocol developed expressly for IrDA transmission. DS785UM1 17-13 Copyright 2007 Cirrus Logic...
Page 610: Introduction
Note: 1. Bits within each DBP are not reordered, but the least significant DBP is transmitted first. Note: 2. A “chip” in the context of the FIR is one time slice in the Position Modulation (PPM) symbol. Figure 17-2. 4PPM Modulation Encoding 17-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 611: Mbps Fir Frame Format
(8 bits) (2045 bytes) (32 bits) Control Preamble Start Flag Address Data CRC-32 Stop Flag (optional) Start Flag |0000|1100|0000|1100|0110|0000|0110|0000| Stop Flag |0000|1100|0000|1100|0000|0110|0000|0110| Preamble |1000|0000|1010|1000|... repeated 16 times Figure 17-4. IrDA (4.0 Mbps) Transmission Format DS785UM1 17-15 Copyright 2007 Cirrus Logic...
Page 612 In a similar manner, the receiver also calculates a CRC for each received data frame and compares the calculated CRC to the expected CRC value contained within the end of each received frame. If the calculated value does not match the expected value, an interrupt is 17-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 613: Functional Description
This repeating pattern is used to identify the first time-slot or beginning of a symbol and resets the two bit chip counter logic, such that the 4 PPM data is properly decoded. DS785UM1 17-17 Copyright 2007 Cirrus Logic...
Page 614: Receive Operation
ROR and EOF bits. The interface will stall in this state until the receiver buffer is emptied. 17-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 615: Transmit Operation
(including the address and control bytes), followed by the stop flag to denote the end of the frame. The transmitter then continuously transmits preambles until data is once again available within the buffer. Once data is available, the transmitter begins transmission of the next frame. DS785UM1 17-19 Copyright 2007 Cirrus Logic...
Page 616: Irda Connectivity
UART2 is the output signal Logical OR of IrDA output signal and UART2 SIR output signal Therefore, to use any IrDA mode, FIR, MIR or SIR, set IonU2. To use UART2 as a UART, clear IonU2. 17-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 617: Irda Integration Information
UARTCLK frequency must accommodate the desired range of baud rates: ≥ × 32 baudrate UARTCLK ≤ × × audrate 65536 b UARTCLK The frequency of UARTCLK must also be within the required error limits for all baud rates to be used. DS785UM1 17-21 Copyright 2007 Cirrus Logic...
Page 618: Bus Bandwidth Requirements
Infrared Mode Bit Rate (bits / second) 115,200 3,600 7,200 Slow MIR 576,000 18,000 36,000 Fast MIR 1,152,000 36,000 72,000 4,000,000 125,000 250,000 Note that the SIR mode bit rate is a worst case value. 17-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 619 EN control bits. LBM: Loopback Mode, for MIR and FIR operation. 0 - Normal operation. 1 - Loopback active, the transmit serial shifter is directly connected to the receive serial shifter. DS785UM1 17-23 Copyright 2007 Cirrus Logic...
Page 620 1 - Enable receiver address match function, do not buffer data unless address is recognized or incoming address contains all ones. RXP: Receive Polarity Control. 0 - Data input is not inverted before decoding. 1 - Data input is inverted before decoding. 17-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 621 This register is used for both MIR and FIR. The AME bit in IrCtrl must be set to enable this function. Frames containing an DS785UM1 17-25 Copyright 2007 Cirrus Logic...
Page 622 0 - Current frame is not completed. 1 - The word in the receive buffer contains the last byte of data within the frame. When the last word in the current frame is read this bit is cleared. 17-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 623 EOF bit set in receive buffer next to the last piece of “good” data received before abort. IrData DATA DATA Address: 0x808B_0010 - Read/Write Default: 0x0000_0000 Definition: IrDA Data Register. Provides access to the transmit and receive buffers used by the MIR and FIR interfaces. DS785UM1 17-27 Copyright 2007 Cirrus Logic...
Page 624 DATA: IrDA transmit payload data. Write to address 0x014, least significant byte is transmitted. Write to address 0x018, least significant two bytes are transmitted. Write to address 0x01C, least significant three bytes are transmitted. 17-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 625 Buffered CRC Error. 0 - No CRC check errors encountered in the last frame. 1 - CRC calculated on the incoming data did not match CRC value contained within the received frame for the last frame. DS785UM1 17-29 Copyright 2007 Cirrus Logic...
Page 626 Byte Count. The total number of valid bytes read by the receiver. IrDMACR RSVD RSVD DMAERR TXDMAE RXDMAE Address: 0x808B_0028 - Read/Write Default: 0x0000_0000 Definition: IrDA DMA Control Register. Bit Descriptions: RSVD: Reserved. Unknown During Read. 17-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 627 The state of SIROUT output from the InfraRed block. Read only. TXD: The state of the TXD input to the InfraRed block from UART2. Read only. RXD: The state of the RXD output from the InfraRed block to UART2. Read only. DS785UM1 17-31 Copyright 2007 Cirrus Logic...
Page 628 FIFO (via the IrData register). This event also triggers the IrRIB to load the IrFlag and byte count. This bit is cleared when the IrRIB register is read. 17-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 629 Bit Descriptions: RSVD: Reserved. Unknown During Read. RFL: RFL mask bit. When high, the MIR RFL status can generate an interrupt. RIL: RIL mask bit. When high, the MIR RIL status can generate an interrupt. DS785UM1 17-33 Copyright 2007 Cirrus Logic...
Page 630 Logical AND of MIR TAB status bit and TAB mask bit. TFC: Logical AND of MIR TFC status bit and TFC mask bit. TFS: Logical AND of MIR TFS status bit and TFS mask bit. 17-34 DS785UM1 Copyright 2007 Cirrus Logic...
Page 631 FIFO (via the IrData register). This event also triggers the IrRIB to load the IrFlag and byte count. This bit is cleared when the IrRIB register is read. DS785UM1 17-35 Copyright 2007 Cirrus Logic...
Page 632 Bit Descriptions: RSVD: Reserved. Unknown During Read. RFL: RFL mask bit. When high, the FIR RFL status can generate an interrupt. RIL: RIL mask bit. When high, the FIR RIL status can generate an interrupt. 17-36 DS785UM1 Copyright 2007 Cirrus Logic...
Page 633 Logical AND of FIR TAB status bit and TAB mask bit. TFC: Logical AND of FIR TFC status bit and TFC mask bit. TFS: Logical AND of FIR TFS status bit and TFS mask bit. DS785UM1 17-37 Copyright 2007 Cirrus Logic...
Page 635 Timer 3 (TC3) has the exact same operation as TC1 and TC2, but it is a 32-bit counter. It has the same register arrangement as TC1 and TC2, providing a load, value, control and clear register. The 16- and 32-bit timer counters can operate in two modes, free running mode or pre-load mode. DS785UM1 18-1 Copyright 2007 Cirrus Logic...
Page 636: Registers
"Timer3Value" 32 bits 0x8081_0088 "Timer3Control" "Timer3Load" 32 bits 0x8081_008C Reserved "Timer3Clear" 1 bit 0x8081_0010 Reserved Reserved 0x8081_0030 Reserved Reserved 0x8081_0040 Reserved Reserved 0x8081_0090 Reserved Reserved a. “Enable” is a field in the "Timer4ValueHigh" register. 18-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 637 Timer Value register to be updated with an undetermined value. Bit Descriptions: RSVD: Reserved. Unknown During Read. Load: Initial load value of the timer. Timer3Load Load Load Address: Timer3 - 0x8081_0080 - Read/Write Reset Value: 0x0000_0000 DS785UM1 18-3 Copyright 2007 Cirrus Logic...
Page 638 The Value location gives the current value of the timer. When the Timer Load register is written to, the Value register is also updated with this Load value. Bit Descriptions: RSVD: Reserved. Unknown During Read. Value: Current value of the timer. Timer3Value Value Value 18-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 639 Reset Value: Not defined. Definition: Writing any value to the Clear location clears an interrupt generated by the timer. Bit Descriptions: RSVD: This register has no readable bits. It is just a write trigger. DS785UM1 18-5 Copyright 2007 Cirrus Logic...
Page 640 1, the timer is in periodic timer mode and when set to “0”, the timer is in free running mode. CLKSEL: When set to “1”, the 508 kHz clock is selected and when set to “0”, the 2 kHz clock is selected. 18-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 641 Timer4ValueHigh is a read-only value and contains the high byte of the Timer4 counter. Note that the Timer4ValueLow register must first be read to store the high byte of the TC4 in Timer4ValueHigh register. DS785UM1 18-7 Copyright 2007 Cirrus Logic...
Page 642 Timers EP93xx User’s Guide Bit Descriptions: RSVD: Reserved. Unknown during a Read operation. Enable: Read/Write. Enable for Timer4. Value: Read only. High Byte of the Timer4 counter. 18-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 643 In either case, if the reset pulse duration is provided or not, the Watchdog counter will start over after the WATCHDOG_RESETn output becomes inactive. This begins a new 250 ms cycle after reset becomes inactive before software must reset the counter. DS785UM1 19-1 Copyright 2007 Cirrus Logic...
Page 644: Chapter 19. Watchdog Timer
7-bit status register is provided in the Watchdog module as WDSTAT. This status value is held through all resets but power on reset. The system can be reset by a three-key reset, a user reset, or a Watchdog reset without losing the contents of this register. 19-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 645: Registers
Watchdog control bits. The ARM Core writes 0x5555 to this half-word to periodically restart the watchdog timer. Writing 0xAA55 to this hword will disable the watchdog timer. Writing 0xAAAA to this hword will re-enable the watchdog timer. DS785UM1 19-3 Copyright 2007 Cirrus Logic...
Page 646 Watchdog Reset Status flip flop. Read only. When “1”, this bit indicates that the last reset was generated because of a watch dog time out. This bit is not cleared by any resets other than power on reset, PWR_RESETn. 19-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 647 PWR_RESETn. The system can be reset by a three-key reset, a user reset, or a watchdog reset without losing the contents of this register. DS785UM1 19-5 Copyright 2007 Cirrus Logic...
Page 648 Watchdog Timer EP93xx User’s Guide 19-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 649: Introduction
RTC is permanently enabled for field use. The compensation value consists of two parts: a counter preload value to act as an integer divider, (RTCSWComp.INT[15:0]), and the number of 32.768 kHz clocks to delete on a periodic interval (RTCSWComp.DEL[4:0]). DS785UM1 20-1 Copyright 2007 Cirrus Logic...
Page 650: Software Compensation
The fractional part of the adjustment is done by deleting clocks from the clock stream feeding the integer counter. The period interval between deleting clocks is 32 seconds. The number of clocks deleted is set by RTCSWComp.DEL[4:0]. 20-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 651: Example - Measured Value Split Into Integer And Fractional Component
1.24 second per month number is better and has been implemented in this device. 20.1.1.6 Real-Time Interrupt To allow a Real Time Interrupt to be generated, VIC2 INT[10] has been connected to the 1 Hz clock. This interrupt should be configured as edge-triggered. DS785UM1 20-3 Copyright 2007 Cirrus Logic...
Page 652: Reset Control
0x8092_0000 - Read Only Default: 0x0000_0000 Definition: RTC Data Register. Contains the 32 bit RTC counter value. This counter is incremented by the 1 Hz clock output from the RTC Trim module. Bit Descriptions: RTCDR: Counter value. 20-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 653 RTC Interrupt Status and End Of Interrupt Register. Writing to this register clears the asserted interrupt. Bit Descriptions: RSVD: Reserved, unknown during read. INTR: Interrupt status, 1 - RTC interrupt is asserted 0 - no interrupt. DS785UM1 20-5 Copyright 2007 Cirrus Logic...
Page 654 0x0000_0000 Definition: RTC Interrupt Control Register. Contains the interrupt enable control bit. Bit Descriptions: RSVD: Reserved, unknown during read. MIE: Match Interrupt Enable, 1 - RTC match interrupt is enabled 0 - interrupt disabled. 20-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 655 If set to 0x0000, no integer divide occurs and no clock pulses are deleted. The value defaults to 0x7FFF which causes the divider to divide by exactly 32,768 to generate a 1 Hz clock. DS785UM1 20-7 Copyright 2007 Cirrus Logic...
Page 656 Real Time Clock With Software Trim EP93xx User’s Guide 20-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 657: Figure 21-1. Architectural Overview Of The I
DMA IF Core RX Channel 0 sdi0 RX Channel 1 sdi1 AMBA APB RX Channel 2 sdi2 lrckr & sckr to each RX channel lrck I2S_AudioClk_Mux Figure 21-1. Architectural Overview of the I S Controller DS785UM1 21-1 Copyright 2007 Cirrus Logic...
Page 658: Table 21-1. I 2 S Controller Input And Output Signals
(SCLK and LRCK) that are generated (see Chapter “Clock Control” on page 5-4 for additional details). The key features of the I S transmitter are: • Three transmit data channels, master or slave mode. 21-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 659: Table 21-3. Transmitter Fifo's
In order to fill a FIFO location, the programmer must write two data words, corresponding to left and right stereo data, to the FIFO. Only when both words are written by the programmer will the FIFO be loaded. Assuming this is the first FIFO write, DS785UM1 21-3 Copyright 2007 Cirrus Logic...
Page 660 This action will ensure that the channels state machines are reset. The next step should be to disable the I S controller, which will result in the FIFO’s being reset. Any samples currently in the FIFO will be lost as a result. 21-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 661: I 2 S Receiver Channel Overview
• Supports 16/24/32 bit word lengths. • Programmable left/right word clock polarity on the serial frame. • Programmable bit clock polarity. • Programmable data validity, that is, data valid on the rising/negative edge of the bit clock. DS785UM1 21-5 Copyright 2007 Cirrus Logic...
Page 662: Receiver Fifo's
The programmer can determine from the Global Control Status register if the FIFO has any valid left / right stereo samples. These samples are obtained from the FIFO via the APB by reading from the I2SRX0Lft and I2SRX0Rt registers. (See “Register 21-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 663: I 2 S Master Clock Generation
S Master Clock Generation The following information is required to generate a set of clocks for the I S controller. The I port i2s_mstr_clk_cfg is used to supply the Syscon block the necessary control information in DS785UM1 21-7 Copyright 2007 Cirrus Logic...
Page 664: Table 21-4. I2Sclkdiv Syscon Register Effect On I
SCLK is not gated. LRCK Speed LRDIV(I2SClkDiv[18:17]) i2s_mstr_clk_cfg[6:5] Audio Slave Mode SLAVE(I2SClkDiv[30]) i2s_mstr_clk_cfg[0] I2SonAC97 (DeviceCfg[6]) or Audio Clock I2SonSSP (DeviceCfg[7]). If either (SCLK, LRCLK) SENA(I2SClkDiv[31]) one is set, it enables the clock Generation Enable generation. 21-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 665: I 2 S Bit Clock Rate Generation
16 than all of the 32x clock pulses are passed. This is shown in Figure 21-2. For other values of nBCG and BCR, the register bit descriptions define the bit clock operation. DS785UM1 21-9 Copyright 2007 Cirrus Logic...
Page 666: Example Of Right Justified Lrck Format
The transmitter generates 4 internal interrupts within the I S controller. Each of these reflect the status of the 3 individual TX FIFOs. These internal interrupts are as follows: • TX0 FIFO empty. • TX1 FIFO empty. 21-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 667 FIFO empty flag will result in an interrupt but for a receiver FIFO empty flag a status bit only is set. The sticky bits refer to bits I2SGlSts[11:6]. A write of zero is required to clear the setting of these bits. DS785UM1 21-11 Copyright 2007 Cirrus Logic...
Page 668: Registers
Right Transmit data register for channel 2 0x8082_0028 I2STXLinCtrlData Line Control data register 0x8082_002C I2STXCtrl Control register 0x8082_0030 I2STXWrdLen Word Length 0x8082_0034 I2STX0En TX0 Channel Enable 0x8082_0038 I2STX1En TX1 Channel Enable 0x8082_003C I2STX2En TX2 Channel Enable 21-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 669 Transmit left data word for channel 0. I2STX0Rt i2s_tx0_right i2s_tx0_right Address: 0x8082_0014 - Read/Write Default: 0x0000_0000 Definition: Transmit right data word for channel 0. Bit Descriptions: i2s_tx0_right: Transmit right data word for channel 0. DS785UM1 21-13 Copyright 2007 Cirrus Logic...
Page 670 Transmit left data word for channel 1. I2STX1Rt i2s_tx1_right i2s_tx1_right Address: 0x8082_001C - Read/Write Default: 0x0000_0000 Definition: Transmit right data word for channel 1. Bit Descriptions: i2s_tx1_right: Transmit right data word for channel 1. 21-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 671 Transmit left data word for channel 2. I2STX2Rt i2s_tx2_right i2s_tx2_right Address: 0x8082_0024 - Read/Write Default: 0x0000_0000 Definition: Transmit right data word for channel 2. Bit Descriptions: i2s_tx2_right: Transmit right data word for channel 2. DS785UM1 21-15 Copyright 2007 Cirrus Logic...
Page 672 If this bit is “0” the I S controller repeats the last sample on underflow. TXDIR: Transmit data shift direction. 0 - MSB first 1 - LSB first I2STXCtrl RSVD RSVD TXUFIE TXEMPTY_int_level Address: 0x8082_002C - Read/Write Default: 0x0000_0000 21-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 673 Transmit Word Length Bit Descriptions: RSVD: Reserved. Unknown During Read. Transmit Word Length. 00 - 16 bit mode 01 - 24 bit mode 10 - 32 bit mode I2STX0En RSVD RSVD i2s_tx0_EN Address: 0x8082_0034 - Read/Write DS785UM1 21-17 Copyright 2007 Cirrus Logic...
Page 674 RSVD RSVD i2s_tx1_EN Address: 0x8082_0038 - Read/Write Default: 0x0000_0000 Definition: TX1 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read. i2s_tx1_EN: TX1 Channel Enable I2STX2En RSVD RSVD i2s_tx2_EN Address: 0x8082_003C - Read/Write Default: 0x0000_0000 21-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 675: I 2 S Rx Registers
Control register 0x8082_0060 I2SRXWrdLen Word Length 0x8082_0064 I2SRX0En RX0 Channel Enable 0x8082_0068 I2SRX1En RX1 Channel Enable 0x8082_006C I2SRX2En RX2 Channel Enable S RX Register Descriptions I2SRX0Lft i2s_rx0_left i2s_rx0_left Address: 0x8082_0040 - Read Only Default: DS785UM1 21-19 Copyright 2007 Cirrus Logic...
Page 676 Receive right data word for channel 0. I2SRX1Lft i2s_rx1_left i2s_rx1_left Address: 0x8082_0048 - Read Only Default: 0x0000_0000 Definition: Receive left data word for channel 1. Bit Descriptions: i2s_rx1_left: Receive left data word for channel 1. 21-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 677 Receive right data word for channel 1. I2SRX2Lft i2s_rx2_left i2s_rx2_left Address: 0x8082_0050 - Read Only Default: 0x0000_0000 Definition: Receive left data word for channel 2. Bit Descriptions: i2s_rx2_left: Receive left data word for channel 2. DS785UM1 21-21 Copyright 2007 Cirrus Logic...
Page 678 Receive Line Control Data Register Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. Left_Right_Justify: Receiver Data word Justification when being received on the SDI line input. 0 - Left justification. 1 - Right justification. 21-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 679 RXFull_int_level: Rx full interrupt level select. 0 - Generate interrupt when FIFO is half full. 1 - Generate interrupt when FIFO is full. I2SRXWrdLen RSVD RSVD Address: 0x8082_0060 - Read/Write Default: 0x0000_0000 Definition: Word Length DS785UM1 21-23 Copyright 2007 Cirrus Logic...
Page 680 RX0 Channel Enable Bit Descriptions: RSVD: Reserved. Unknown During Read. Must be written as “0”. i2s_rx0_EN: RX0 Channel Enable I2SRX1En RSVD RSVD i2s_rx1_EN Address: 0x8082_0068 - Read/Write Default: 0x0000_0000 efinition: RX1 Channel Enable 21-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 681: I 2 S Configuration And Status Registers
Receiver clock configuration 0x8082_0004 I2SRXClkCfg register S Global Status register. This 0x8082_0008 0x12492 I2SGlSts reflects the status of the 3 RX FIFOs and the 3 TX FIFOs. 0x8082_000C I2SGlCtrl S Global Control register. DS785UM1 21-25 Copyright 2007 Cirrus Logic...
Page 682 If this bit = 0 and the word length is 24, the last 8 cycles are gated off in each word. If this bit = 1 and the word length is 24, the last 8 cycles are not gated off in each word. 21-26 DS785UM1 Copyright 2007 Cirrus Logic...
Page 683 1 - if lrckt is low, then it is the right word, if lrckt is high, then it is the left word. I2SRXClkCfg RSVD RSVD i2s_rx_bcr i2s_rx_nbcg i2s_mstr i2s_rrel i2s_rckp i2s_rlrs Address: 0x8082_0004 - Read/Write Default: 0x0000_0000 Definition: Receiver clock configuration register. Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 21-27 Copyright 2007 Cirrus Logic...
Page 684 0 - if lrckr is low then it is the left word, if lrckr is high then it is the right word. 1 - if lrckr is low then it is the right word, if lrckr is high then it is the left word. 21-28 DS785UM1 Copyright 2007 Cirrus Logic...
Page 685: I 2 S Global Status Registers
= 1, the tx0 FIFO is full and an attempt has been made to write data to it by the APB or DMA. This bit is cleared by writing a 0 to it. DS785UM1 21-29 Copyright 2007 Cirrus Logic...
Page 686 = 1, FIFO is full, otherwise not full tx2_fifo_empty: when = 1, FIFO is empty, otherwise not empty tx2_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half empty rx2_fifo_full: when = 1, FIFO is full, otherwise not full 21-30 DS785UM1 Copyright 2007 Cirrus Logic...
Page 687 The transmit section will control the clock configuration during loopback the same as if full- duplex operation was used. DS785UM1 21-31 Copyright 2007 Cirrus Logic...
Page 688 S Controller EP93xx User’s Guide 21-32 DS785UM1 Copyright 2007 Cirrus Logic...
Page 689: Table 22-1. Ac'97 Input And Output Signals
For example, all audio data are at the same sampling rate DS785UM1 22-1 Copyright 2007 Cirrus Logic...
Page 690: Chapter 22. Ac'97 Controller
If the external codec does not support the Data Request Disable bits/Variable Rate Extension the bits will always be “0” meaning a sample rate of 48 kHz. As slots 1 and 2 are always 22-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 691: Interrupts
If the transmit FIFO is disabled (has a depth of one location) and there is no data present in the transmitters single location, the transmit interrupt is asserted high. The transmit interrupt is cleared by performing a single write to the transmit FIFO. DS785UM1 22-3 Copyright 2007 Cirrus Logic...
Page 692: Rtis
It is up to the interrupt service routine to read the AC97S12Data register in order to clear this interrupt. The external codec’s register (0x54) GPIO pin Status reflects the state of all of the GPIO pins. 22-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 693: Gpiotxcomplete
Read/Write AC97IE1 Interrupt Enable 0x8088_001C Reserved 0x8088_0020 Read/Write AC97DR2 Data read or written from/to FIFO2 0x8088_0024 Read/Write AC97RXCR2 Control register for receive 0x8088_0028 Read/Write AC97TXCR2 Control register for transmit 0x8088_002C Read AC97SR2 Status register DS785UM1 22-5 Copyright 2007 Cirrus Logic...
Page 694 Main Control register 0x8088_00A0 Read/Write AC97Reset RESET control register. 0x8088_00A4 Read/Write AC97SYNC SYNC control register. 0x8088_00A8 Read AC97GCIS Global channel FIFO interrupt status register. Register Descriptions AC97DRx RSVD / DATA (See Definition, below.) DATA DATA 22-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 695 FIFO buffer along with the overrun data value. AC97RXCRx RSVD FDIS RSIZE RX12 RX11 RX10 Address: AC97RXCR1 - 0x8088_0004 - Read/Write AC97RXCR2 - 0x8088_0024 - Read/Write AC97RXCR3 - 0x8088_0044 - Read/Write AC97RXCR4 - 0x8088_0064 - Read/Write DS785UM1 22-7 Copyright 2007 Cirrus Logic...
Page 696 See Table 22-3. 0 - The data is justified into separate 32 bit words 1 - The two data words are compacted into one 32-bit word for reading by the CPU. 22-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 697: Table 22-3. Interaction Between Rsize And Cm
FIFO stores SLOT3 data RX2: FIFO stores SLOT2 data RX1: FIFO stores SLOT1 data REN: A “1” written to this bit enables the receive for this FIFO and enables the PCLK for the respective channel. DS785UM1 22-9 Copyright 2007 Cirrus Logic...
Page 698 Bit Descriptions: RSVD: Reserved. Unknown During Read. FDIS: FIFO Disable 0 - The FIFO buffers are Enabled (FIFO mode). 1 - The FIFO is disabled (character mode). That is, the FIFO becomes 1-byte-deep holding registers. 22-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 699: Table 22-4. Interaction Between Rsize And Cm Bits
FIFO stores SLOT6 data TX5: FIFO stores SLOT5 data TX4: FIFO stores SLOT4 data TX3: FIFO stores SLOT3 data TX2: FIFO contains SLOT2 data (only use if sampling rate is 48 kHz). Takes precedence over AC97S2Data. DS785UM1 22-11 Copyright 2007 Cirrus Logic...
Page 700 RX Overrun Error - This bit is set to “1” if an overrun error has been detected. This bit is set to “1” if data is received and the FIFO is already full. This bit is cleared to “0” by reading the AC97DR register. 22-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 701 RX Interrupt Status - This bit is set to “1” if the receive FIFO becomes half full. TIS: TX Interrupt Status - This bit is set to “1” if the transmit FIFO becomes half empty. DS785UM1 22-13 Copyright 2007 Cirrus Logic...
Page 702 RX Timeout Interrupt Status - If this bit is set to “1”, the timeout FIFO interrupt is asserted. TCIS: TX complete Interrupt Status - If this bit is set to “1”, the transmit FIFO complete interrupt is asserted. 22-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 703 0x8088_0080 - Read/Write Definition: Slot 1 Data Register. The AC97S1Data register is a read / write register. When a write has occurred to this register, the data contained within it is sent on the DS785UM1 22-15 Copyright 2007 Cirrus Logic...
Page 704 Slot 2 Data Register. The AC97S2Data register is a read / write register. When a write has occurred to this register, the data contained within it will be sent on the next available frame in SLOT2. In order to perform a write to the external 22-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 705 SLOT 12. Bit 0 is monitored to see if a GPIOINT has occurred. Write operation: Write data value to transmit on slot 12 on next available frame. Once the data has been transmitted it will marked as invalid. DS785UM1 22-17 Copyright 2007 Cirrus Logic...
Page 706 Reading the data in the AC97S2Data register clears this bit. SLOT1TXCOMPLETE:Set when the AC97S1Data register has completed transmission. This bit is cleared when data is written to the AC97S1Data register to be transmitted. 22-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 707 GPIOTXCOMPLETE:If this bit is set to “1”, the GPIOTXCOMPLETE interrupt is asserted. SLOT2RXVALID: If this bit is set to “1”, SLOT2RXVALID interrupt is asserted. SLOT1TXCOMPLETE:If this bit is set to “1”, SLOT1TXCOMPLETE interrupt is asserted. DS785UM1 22-19 Copyright 2007 Cirrus Logic...
Page 708 SLOT2RXVALID: If this bit is set to “1”, SLOT2RXVALID interrupt is enabled. SLOT1TXCOMPLETE:If this bit is set to “1”, SLOT1TXCOMPLETE interrupt is enabled. AC97EOI RSVD CODECREADY WINT Address: 0x8088_0098 - Write Only 22-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 709 Defaults to “0” when reset. Ensure this bit is always “0” for normal operation. AC97IFE: AC97IF Enable: If this bit is set the AC’97 is enabled. Defaults to “0” on reset. When set to “0”, all FIFOs are reset to “0”. DS785UM1 22-21 Copyright 2007 Cirrus Logic...
Page 710 2.9491 MHz clock (0.339 µs x 5 = 1.695 µs maximum reset pulse and 1.356 µs minimum reset pulse using this 2.9491 MHz clock). After which this bit is zeroed. 22-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 711 2.9491 MHz (0.339 µs x 5 = 1.695 µs maximum SYNC pulse and 1.356 µs minimum SYNC pulse using this clock). After which this bit is zeroed, allowing the SYNC to be controlled via the BITCLK counter. DS785UM1 22-23 Copyright 2007 Cirrus Logic...
Page 712 AC97GIS: Copy of the AC97GIS register AC97ISR4: Copy of the AC97ISR 4 register AC97ISR3: Copy of the AC97ISR 3 register AC97ISR2: Copy of the AC97ISR 2 register AC97ISR1: Copy of the AC97ISR 1 register 22-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 713: Introduction
• Half duplex transfer using 8-bit control message • Texas Instrument synchronous serial interface features: • Full duplex four-wire synchronous transfer • Transmit data pin can be in high impedance state when not transmitting DS785UM1 23-1 Copyright 2007 Cirrus Logic...
Page 714: Ssp Pin Multiplex
You can either prime the transmit FIFO, by writing up to eight 16-bit values when the SSP is disabled, or allow the transmit FIFO service request to interrupt the CPU. Once enabled, transmission or reception of data begins on the transmit (SSPTXD) and receive (SSPRXD) pins. 23-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 715: Master/Slave Mode
8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. DS785UM1 23-3 Copyright 2007 Cirrus Logic...
Page 716: Texas Instruments Synchronous Serial Frame Format
Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. SCLKOUT / SCLKIN SFRMOUT / SFRMIN SSPTXD / MS B SSPRXD 4 t o 16 bi t s SSPOE (=0) Figure 23-2. TI Synchronous Serial Frame Format (Continuous Transfer) 23-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 717: Motorola Spi Frame Format
SCLKIN SFRMOUT / SFRMIN SSPRXD MS B LS B 4 t o 16 bi t s SSPOE MS B LS B SSPTXD Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0 DS785UM1 23-5 Copyright 2007 Cirrus Logic...
Page 718: Figure 23-4. Motorola Spi Frame Format (Continuous Transfer) With Spo=0 And Sph=0
On completion of the continuous transfer, the SFRMOUT pin is returned to its idle state one SCLKOUT period after the last bit has been captured. 23-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 719: Motorola Spi Format With Spo=0, Sph=1
HIGH state one SCLKOUT period after the last bit has been captured. For continuous back-to-back transfers, the SFRMOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer. DS785UM1 23-7 Copyright 2007 Cirrus Logic...
Page 720: Motorola Spi Format With Spo=1, Sph=0
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling the SCLKOUT pad (active LOW enable) • when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling the SCLKOUT pad (active LOW enable). 23-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 721: Motorola Spi Format With Spo=1, Sph=1
23-8, Q is an undefined signal. In this configuration, during idle periods: • the SCLKOUT signal is forced HIGH • SFRMOUT is forced HIGH • the transmit data line SSPTXD is arbitrarily forced LOW DS785UM1 23-9 Copyright 2007 Cirrus Logic...
Page 722: National Semiconductor Microwire Frame Format
SC LK clk_low SFR M M SB L SB SSPTXD 8-bit control SSPR XD M S B 4 to 16 bits output data Figure 23-9. Microwire Frame Format (Single Transfer) 23-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 723 Each of the received values is transferred from the receive shifter on the falling edge SCLKOUT, after the LSB of the frame has been latched into the SSP. DS785UM1 23-11 Copyright 2007 Cirrus Logic...
Page 724: Setup And Hold Time Requirements On Sfrmin With Respect To Sclkin In Microwire Mode
S S P R X D F irst R X d ata b it to b e clkm ax sam p led b y S S P slave Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements 23-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 725: Registers
RSVD Address: 0x808A_0000 - Read/Write Default: 0x0000_0000 Definition: SSPCR0 is the control register 0 and contains four different bit fields, which control various functions within the SSP. Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 23-13 Copyright 2007 Cirrus Logic...
Page 726 1001 - 10-bit data 1010 - 11-bit data 1011 - 12-bit data 1100 - 13-bit data 1101 - 14-bit data 1110 - 15-bit data 1111 - 16-bit data SSPCR1 RSVD RSVD RORIE Address: 0x808A_0004 - Read/Write 23-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 727 SSPRORINTR interrupt. TIE: Transmit FIFO interrupt enable: 0 - Transmit FIFO half-full or less condition does not generate the SSPTXINTR interrupt. 1 - Transmit FIFO half-full or less condition generates the SSPTXINTR interrupt. DS785UM1 23-15 Copyright 2007 Cirrus Logic...
Page 728 FIFO and the receive FIFO are not cleared even when SSE is set to zero. This allows the software to fill the transmit FIFO before enabling the SSP. Bit Descriptions: RSVD: Reserved. Unknown During Read. 23-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 729 Transmit FIFO not full (read-only): 0 - Transmit FIFO is full. 1 - Transmit FIFO is not full. TFE: Transmit FIFO empty (read-only): 0 - Transmit FIFO is not empty 1 - Transmit FIFO is empty DS785UM1 23-17 Copyright 2007 Cirrus Logic...
Page 730 0 SSPIIR / SSPICR RSVD RSVD RORIS Address: 0x808A_0014 - Read Only Note: A write to this register clears the receive overrun interrupt, regardless of the data value written. Default: 0x0000_0000 23-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 731 0 - SSPRXINTR is not asserted indicating that the receive FIFO is less than half full. 1 - SSPRXINTR is asserted indicating that the receive FIFO is more than half full (4 or more half words present in FIFO) DS785UM1 23-19 Copyright 2007 Cirrus Logic...
Page 732 Synchronous Serial Port EP93xx User’s Guide 23-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 733: Introduction
(in terms of number of PWM clock cycles), and the duration of high-phase of the pulse (set in terms of the number of PWM clock cycles). DS785UM1 24-1 Copyright 2007 Cirrus Logic...
Page 734: Example
Wait for PWM to finish current cycle ----------------- Program TC value with 659 (decimal) PWMxTermCnt 0x0293 Program DC value with 131 (decimal) PWMxDutyCycle 0x0083 Program PWM output to invert PWMxInvert 0x0001 Enable/Start PWM PWMxEn 0x0001 24-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 735: Dynamic Programming (Pwm Is Running) Example
PWM1 Invert 0x0000 Note: All pwmout outputs will drive a logical “0” during reset. Coming out of reset, it will continue to drive a logical “0”, and the PWM will be in halt mode. DS785UM1 24-3 Copyright 2007 Cirrus Logic...
Page 736 PWM cycle to prevent any output glitches or errors. Reading the register reflects what was written to it, not the state of the counter. PWMxDutyCycle PWM_DC Address: PWM0DutyCycle: 0x8091_0004 - Read/Write PWM1DutyCycle: 0x8091_0024 - Read/Write Default: 0x0000_0000 Definition: PWMx Duty Cycle 24-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 737 1 - PWM is Enabled. When in normal mode writing a one will start the PWM. PWMxTermCnt is updated with its new buffered value. PWMxDutyCycle is updated with its new buffered value. PWMxInvert RSVD Address: PWM0Invert: 0x8091_000C - Read/Write PWM1Invert: 0x8091_002C - Read/Write DS785UM1 24-5 Copyright 2007 Cirrus Logic...
Page 738 PWM_INV invert bit. PULSE 1 PULSE 2 PULSE 3 clk_pwm pwmout PWM_INV = 0 Duty Cycle = pwmout PWM_INV = 1 Duty Cycle = Figure 24-1. PWM_INV Example 24-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 739: Introduction
To understand the controller operation, it is first important to understand the electrical implementation of touch screen technologies. The schematics for various resistive touch screen technologies are shown in Figure 25-1. When the front and back indium-tin-oxide layers are pressed together, a resistive contact is made. DS785UM1 25-1 Copyright 2007 Cirrus Logic...
Page 740 Y lines, and by then measuring a voltage driven between the bus bars on the Y-axis layer through either or both of the X lines. By comparing these voltages to values determined during calibration, the location of the touch can be determined. 25-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 741: Table 25-1. Switch Definitions And Logical Safeguards To Prevent Physical Damage
SW9 = HIGH and SW26 = LOW and SW24 = LOW Bit 10 AGND ADC REF- Bit 11 AGND Bit 12 AGND Bit 13 AGND Bit 14 AGND Bit 15 AGND Bit 16 AGND Bit 17 AGND DS785UM1 25-3 Copyright 2007 Cirrus Logic...
Page 742 TSSetup2.SIGND bit should be set. The flow chart in Figure 25-4 demonstrates the sample process used for determining touch input on a touch screen. The ARM Core must load all of the setup registers for the touch 25-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 743: Figure 25-2. 8-Wire Resistive Interface Switching Diagram
SW27 SW27 SW27 REF- REF- REF- REF- SW15 SW15 SW15 SW15 SW16 SW16 SW16 SW16 SW10 SW10 SW10 SW10 SW17 SW17 SW17 SW17 SW18 SW18 SW18 SW18 Figure 25-2. 8-Wire Resistive Interface Switching Diagram DS785UM1 25-5 Copyright 2007 Cirrus Logic...
Page 744: Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram
SW27 SW27 REF- REF- REF- REF- SW15 SW15 SW15 SW15 SW16 SW16 SW16 SW16 SW10 SW10 SW10 SW10 SW17 SW17 SW17 SW17 SW18 SW18 SW18 SW18 Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram 25-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 745: Table 25-2. Touch Screen Switch Register Configurations
2, 3, 4, or 5 places to divide by the number of samples as determined by the NSMP value in the TSSetup register. This generates the average for the sample set for a new X value. DS785UM1 25-7 Copyright 2007 Cirrus Logic...
Page 746 If the difference is less than this value, no Y action is taken and the algorithm continues by checking the X interrupt pending flag. If this flag is set the Y value is stored in the Y last register and the interrupt to the ARM Core is generated. 25-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 747: Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart
GREATER THAN YMAX? ABS(X-XLAST) SET INTERRUPT GREATER THAN YLAST = Y XMAX? SET Y INT PENDING YLAST = Y SET X INT PENDING XLAST = X Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart DS785UM1 25-9 Copyright 2007 Cirrus Logic...
Page 748: Five-Wire And Seven-Wire Operation
The sY+ feedback line is still used as a Wiper input to the A / D converter. The register values TSDischarge, TSXSample, and TSYSample are derived from the switch positions in the diagram. They are provided in Table 25-2. 25-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 749: Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram
SW15 SW15 SW15 SW16 SW16 SW16 SW16 SW10 SW10 SW10 SW10 SW17 SW17 SW17 SW17 SW18 SW18 SW18 SW18 5 WIRE ANALOG RESISTIVE INTERFACE SWITCHING DIAGRAM Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram DS785UM1 25-11 Copyright 2007 Cirrus Logic...
Page 750: Direct Operation
Entering the low-power state with interrupts enabled may trigger false interrupts. 25-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 751: Measuring Analog Input With The Touch Screen Controls Disabled
4-wire or 5-wire touch screens can be read from the APB bus by temporarily disabling the touch screen controller. Please note that the initial read should be viewed as a convert command where the data provided is stale and should be discarded. DS785UM1 25-13 Copyright 2007 Cirrus Logic...
Page 752: Figure 25-8. Other Switching Diagrams
SW25 SW25 SW26 SW26 SW26 Used Used SW27 Used SW27 SW27 REF- REF- REF- SW15 SW15 SW15 SW16 SW16 SW16 SW10 SW10 SW10 SW17 SW17 SW17 SW18 SW18 SW18 Figure 25-8. Other Switching Diagrams 25-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 753: Measuring Touch Screen Resistance
SW26 SW26 SW26 Not used SW27 SW27 Not used SW27 REF- REF- REF- SW15 SW15 SW15 SW16 SW16 SW16 SW10 SW10 SW10 SW17 SW17 SW17 SW18 SW18 SW18 Figure 25-9. Measure Resistance Switching Diagram DS785UM1 25-15 Copyright 2007 Cirrus Logic...
Page 754: Polled And Interrupt-Driven Modes
Touch Screen ADC X axis analog bias output. Touch Screen ADC Y axis analog bias output. Touch Screen ADC X axis voltage feedback inputs. Touch Screen ADC Y axis voltage feedback inputs. ADC_GND Touch Screen ADC ground 25-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 755: Registers
Since the least significant bytes of the address bus are not decoded, byte and half word accesses are not allowed and may have unpredictable results. Register Descriptions TSSetup TDTCT RSVD NSMP SDLY Address: 0x8090_0000 Default: 0x0000_0000 DS785UM1 25-17 Copyright 2007 Cirrus Logic...
Page 756 Enables the touch screen scanning state machine. 0 - Disabled. 1 - Enabled. DLY: Defines the amount of settling time between changes to the touch screen drive conditions from 3 to 1024 μs assuming a 1 MHz clock. 25-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 757 ARM Core. The x-y box definition can be up to 512 x 512 (+/-256). TSXYResult RSVD AD_X Address: 0x8090_0008 Default: 0x0000_0000 Definition: Analog Touch screen X and Y result Register. DS785UM1 25-19 Copyright 2007 Cirrus Logic...
Page 758 Analog switch control Registers. Bit Descriptions: RSVD: Reserved. Unknown during read. SCTL[29]: Analog switch control value for direct analog switch control only (TSDirect) when the touch screen controller is disabled. Controls DAC routing to ADC input. 25-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 759 Since the software lock only remains unlocked for the next block cycle, this test must be performed on two consecutive cycles using the ARM lock instruction prefix. The contents of SWLCK[7:1] are unknown during a read operation. DS785UM1 25-21 Copyright 2007 Cirrus Logic...
Page 760 Deviation Error Interrupt Enable. Setting this bit high causes an interrupt when the sample deviation check fails 255 times for either the X or Y axis. The DTMEN bit must be high for this bit to be effective. 25-22 DS785UM1 Copyright 2007 Cirrus Logic...
Page 761 It may be triggered from an off-screen unpressed stable value. Writing a “0” to this bit will clear the touch interrupt. This bit may be written high for test purposes. DS785UM1 25-23 Copyright 2007 Cirrus Logic...
Page 762 Analog Touch Screen Interface EP93xx User’s Guide 25-24 DS785UM1 Copyright 2007 Cirrus Logic...
Page 763: Introduction
3 Key Reset Key Detector 3 Key Reset Column lines Equal Compare Inactive Pipeline Debounce Counter Diagnostics Temp Key Regs Key Regs Row lines Row/Collumn Row Decoder Precounter Counter Figure 26-1. Key Array Block Diagram DS785UM1 26-1 Copyright 2007 Cirrus Logic...
Page 764: Theory Of Operation
When more than 2 keys are pressed, it is possible to detect apparent keys. Apparent keys look like actual pressed keys to the device but are not. An example of an apparent key is described in “Apparent Key Detection”. 26-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 765: Apparent Key Detection
• An apparent key address of 0x00 at (ROW0, COL0)] • An actual key address of 0x03 at (ROW0, COL3) • No press for address 0x18 at (ROW3, COL0) DS785UM1 26-3 Copyright 2007 Cirrus Logic...
Page 766: Figure 26-3. Apparent Key 00H
KEY 33H KEY 34H KEY 35H KEY 36H KEY 37H ROW 6 KEY 38H KEY 39H KEY 3AH KEY 3BH KEY 3CH KEY 3DH KEY 3EH KEY 3FH ROW 7 Figure 26-3. Apparent Key 00H 26-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 767: Scan And Debounce
If an interrupt is ignored, then a subsequent interrupt will be pending until the first interrupt is serviced. If further keypad activity occurs after an interrupt is pending then the most recent de-bounced and decoded event will become pending and the previous pending conditions will be lost. DS785UM1 26-5 Copyright 2007 Cirrus Logic...
Page 768: Low Power Mode
Note: Key scan controller registers are intended to be word accessed only. Since the least significant bytes of the address bus are not decoded, byte and half word accesses are not allowed and may have unpredictable results. Register Descriptions KeyScanInit RSVD DBNC DIS3KY DIAG BACK PRSCL 26-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 769 RC_COUNT is advanced by 8 counts when EN is active. The effect is that only column 0 is checked in each row. This test mode allows a faster test of the ROW pins. Not Assigned. These bits will read back the value written. DS785UM1 26-7 Copyright 2007 Cirrus Logic...
Page 770 Diagnostic key value. When diagnostic mode is enabled (KeyScanInit.DIAG high) and this register is written, the Row Column scan value is used to directly control the chip key matrix scan drivers and receivers. Results are read back via the KeyRegister.K bit. 26-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 771: Introduction
2 pins that are shared with the EGPIO block. The INT type indicates the pin using one of pins. The NI type indicates an IDE signal that is not supported. All others are dedicated pins. DS785UM1 27-1 Copyright 2007 Cirrus Logic...
Page 772: Diagrams And State Machines
DMA acknowledge to DMARQ to initiate DMA transfers Signal to indicate that a device is active, or that Device 1 is DASPn GPIO present DMARQ GPIO DMA request for DMA to and from the controller INTRQ Device interrupt 27-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 773: Pio Operations
PIO Mode 2 - Delay for 290 ns. PIO Mode 3 - Delay for 80 ns PIO Mode 4 - Delay for 70 ns 5. Bring DIORn low. 6. Read IDE Data in the register. DS785UM1 27-3 Copyright 2007 Cirrus Logic...
Page 774: Mdma Operations
For MDMA operations, DMA commands are set up using PIO operations by the host. The registers IDEMDMADataOut and IDEMDMADataIn act as the 1-deep buffer for write and read operations respectively. The state machine sets up the necessary signals including the DMA request to the DMA controller. 27-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 775: Udma Operations
DMA controller will try to keep the input read buffer empty. For host write operations the DMA controller will try to keep the output write buffer at least half full. If the DMA Transfer State DS785UM1 27-5 Copyright 2007 Cirrus Logic...
Page 776: Udma Example
DSTROBE too quickly for the host to keep up with latching the data from DD bus, based on the synchronized version of DSTROBE. There is a lower limit for AHB clock speed, where lowering the speed further cannot guarantee correct 27-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 777: Dma Request Latency
The assumption is that the deassertion should follow an AHB bus command (read or write) in HCLK cycle 1. DS785UM1 27-7 Copyright 2007 Cirrus Logic...
Page 778: Ide Dma Programming Considerations
Table 27-3 Table 27-4. Quad-word bursts are not allowed. 27.2.7.3.2 Multi-word DMA Follow the wait-state number listed in the wait-state table in Table 27-3 Table 27-4. Quad- word bursts are not allowed. 27-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 779: Ide Package Dependency
PIO Mode 1 5.22 MBps PIO Mode 2 8.33 MBps PIO Mode 3 11.11 MBps PIO Mode 4 16.67 MBps MDMA Mode 0 4.17 MBps MDMA Mode 1 13.33 MBps MDMA Mode 2 16.67 MBps DS785UM1 27-9 Copyright 2007 Cirrus Logic...
Page 780: Registers
0x0000_0063 Definition: IDE Control Register. This register is used for IDE PIO control operations. IORDY, INTRQ, DMARQ, and DASPn reflect external pins. Their reset state can vary depending on system implementation and system configuration. 27-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 781 0x0000_0000 Definition: IDE Configuration Register. Bit Descriptions: RSVD: Reserved. Unknown during read, ignored during write. IDEEN: IDE master enable. PIO: Polled IO operation selection. MDMA: Multiword DMA operation selection. UDMA: Ultra DMA operation selection. DS785UM1 27-11 Copyright 2007 Cirrus Logic...
Page 782 Enable Multiword DMA operation. 1 - to start MDMA 0 - to terminate MDMA by the host. RWOP: Read or write operation selection: 0 - Read 1 - Write. IDEUDMAOp RSVD RSVD RWOP Address: 0x800A_000C - Read/Write 27-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 783 Any write in these two operation modes is ignored. Bit Descriptions: IDEDD: IDE output data in PIO writes (read write), data in output buffer in MDMA and data at the tail of output buffer in UDMA mode (read only). DS785UM1 27-13 Copyright 2007 Cirrus Logic...
Page 784 In MDMA data-out operations, this register contains the data in the output buffer to be transferred to the device. The data is written into this register by the DMA controller. This register should only be addressed and written by the 27-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 785 0x800A_0020 - Write Only (should be written by the DMA controller only) Default: 0x0000_0000 Definition: In UDMA data-out operations, this register contains the data at the tail of the output buffer to be written by the DMA controller. This register should only be DS785UM1 27-15 Copyright 2007 Cirrus Logic...
Page 786 IDE input data at the head of the input buffer in UDMA mode. IDEUDMASts RSVD RSVD SBUSY INTide DMAide RSVD DSDD DMARQ DDOE STOP HSHD CS1n CS0n Address: 0x800A_0028 - Read Only Default: 0x0000_0000 27-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 787 INT line generated by UDMA because of errors in the state machine. SBUSY: UDMA state machine busy, not in idle state. NDO: Error for data-out not completed. NDI: Error for data-in not completed. N4X: Error for data transferred not multiples of four 32-bit words. DS785UM1 27-17 Copyright 2007 Cirrus Logic...
Page 788 Reset UDMA read buffer pointer to 0. RRDR: Reset UDMA read DMA request. IDEUDMAWrBufSts RSVD FULL NFULL EMPTY TPTR HPTR Address: 0x800A_0030 - Read Only Default: 0x0000_0100 Definition: Status register for UDMA write buffer. 27-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 789 Half or more entries in read buffer filled status. NFULL: Read buffer near full status. FULL: Read buffer full status. CRC: CRC result for data-in operation. Reset back to 0x4ABA after finishing UDMA operation. DS785UM1 27-19 Copyright 2007 Cirrus Logic...
Page 790 IDE Interface EP93xx User’s Guide 27-20 DS785UM1 Copyright 2007 Cirrus Logic...
Page 791: Chapter 28. Gpio Interface
The control of an individual pin is determined in a bit-slice fashion across all registers for that port; only a single bit at a particular index from each register affects or is affected by that pin. DS785UM1 28-1 Copyright 2007 Cirrus Logic...
Page 792: Figure 28-1. System Level Gpio Connectivity
READY Controls MUX_IO Port F MCBVD2 Control DATA MCBVD1 MCCD2 MCCD1 Controls MUX_IO Port G DD[15:12] Control DATA SLA[1:0] EEDAT EECLK Controls MUX_IO Port H DD[7:0] Control DATA Figure 28-1. System Level GPIO Connectivity 28-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 793: Memory Map
• Interrupt Status registers (IntStsA, IntStsB, IntStsF) provide the status of any pending unmasked interrupt. • Raw Interrupt Status registers (RawIntStsA, RawIntStsB, RawIntStsF) provide the status of any pending interrupt regardless of masking. DS785UM1 28-3 Copyright 2007 Cirrus Logic...
Page 794: Figure 28-2. Signal Connections Within The Standard Gpio Port Control Logic (Ports C, D, E, G, H)
Standard GPIO Ports C, D, E, G, and H OE[7:0] DATA[7:0] DATA TISR to PRDATA[7:0] EP[7:0] Register TESTRDSEL Read TESTINPSEL Select Figure 28-2. Signal Connections Within the Standard GPIO Port Control Logic (Ports C, D, E, G, H) 28-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 795: Reset
G[3:2] bits are used for SLA[1:0] outputs and are set to drive low. Port G[1:0] bits are used for EEDAT and EECLK respectively and are set up as inputs. All interrupt control and debounce registers are cleared. DS785UM1 28-5 Copyright 2007 Cirrus Logic...
Page 796: Gpio Pin Map
Port G1 Port G1 EEDAT ROW[7:0] Port C ROW[7:0] COL[7:0]6 COL[7:0] Port D 1. GRLED is the Green LED pin. 2. RDLED is the Red LED pin. 3. EECLK is the EEPROM clock pin. 28-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 797: Table 28-3. Ep9312 Gpio Port To Pin Map
4. RDLED is the Red LED pin. 5. EECLK is the EEPROM clock pin. 6. EEDAT is the EEPROM data pin. 7. ROW[7:0] are the Key Matrix row pins. 8. COL[7:0] are the Key Matrix column pins. DS785UM1 28-7 Copyright 2007 Cirrus Logic...
Page 798: Table 28-4. Ep9315 Gpio Port To Pin Map
5. GRLED is the Green LED pin. 6. RDLED is the Red LED pin. 7. EECLK is the EEPROM clock pin. 8. EEDAT is the EEPROM data pin. 9. ROW[7:0] are the Key Matrix row pins. 28-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 799: Registers
0x8084_0030 PFDR PFDR Note 1 0x8084_0034 PFDDR PFDDR 0x00 0x8084_0038 PGDR PGDR Note 1 0x8084_003C PGDDR PGDDR 0x0C 0x8084_0040 PHDR PHDR Note 1 0x8084_0044 PHDDR PHDDR 0x00 0x8084_0048 RSVD RSVD 0x8084_004C GPIOFIntType1 GPIOFIntType1 0x00 DS785UM1 28-9 Copyright 2007 Cirrus Logic...
Page 800 3. The RAWSTATUSx registers have pin dependent default read states. The interrupt control registers default to low level sensitive interrupt on reset. Therefore the external pin state will ripple through the interrupt logic to determine the RAWSTATUSx default. Register Descriptions PxDR RSVD RSVD PxDATA Address: 28-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 801 All bits are cleared by a system reset. (“X.” stands for a letter, A through H.) Bit Descriptions: RSVD: Reserved. Unknown During Read. DS785UM1 28-11 Copyright 2007 Cirrus Logic...
Page 802 The interrupt type is controlled by the GPIOxINTTYPE1/2 registers described in the following sections. Bit Descriptions: RSVD: Reserved. Unknown During Read. PxINT: Port x interrupt enables. GPIOxIntType1 RSVD RSVD PxINTE Address: GPIOAIntType1: 0x8084_0090 - Read/Write GPIOBIntType1: 0x8084_00AC - Read/Write GPIOFIntType1: 0x8084_004C - Read/Write Definition: 28-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 803 GPIOxINTTYPE1 bit should set high and low for level sensitive interrupts. All bits are cleared by a system reset. Bit Descriptions: RSVD: Reserved. Unknown During Read. PxINTR: Determines which type of edge or level sensitive interrupt may occur. DS785UM1 28-13 Copyright 2007 Cirrus Logic...
Page 804 Debouncing is implemented by passing the input signal through a 2-bit shift register clocked by a 128 Hz clock. 28-14 DS785UM1 Copyright 2007 Cirrus Logic...
Page 805 When edge triggered, it is cleared by writing the corresponding bit in GPIOxEOI. Note that the value of a bit is a debounced value if debouncing is enabled. Bit Descriptions: RSVD: Reserved. Unknown During Read. PxINTRS: Raw Interrupt Status. IntStsX RSVD RSVD PxINTS Address: DS785UM1 28-15 Copyright 2007 Cirrus Logic...
Page 806 Bits whose corresponding interrupt is not enabled report “0”. Bit Descriptions: RSVD: Reserved. Unknown During Read. PxINTS: Masked Interrupt Status. EEDrive RSVD RSVD DATOD CLKOD Address: 0x8084_00C8 - Read/Write 28-16 DS785UM1 Copyright 2007 Cirrus Logic...
Page 807 When clear, the corresponding pin is a normal CMOS driver. DATOD controls the EEDAT pin. CLKOD controls the EECLK pin. Bit Descriptions: RSVD: Reserved. Unknown During Read. DATOD: Defines the EEDAT pin output driver. CLKOD: Defines the EECLK pin output driver. DS785UM1 28-17 Copyright 2007 Cirrus Logic...
Page 808 GPIO Interface EP93xx User’s Guide 28-18 DS785UM1 Copyright 2007 Cirrus Logic...
Page 809: Chapter 29. Security
• Multiple security vendors can co-exist in the same system. • JTAG functionality is disabled when security is enabled. • External boot is disabled when security is enabled. 29.3 Contact Information Contact Cirrus Logic at www.cirrus.com for additional information regarding security features. DS785UM1 29-1 Copyright 2007 Cirrus Logic...
Page 810: Registers
Note: Most Security registers are not documented in this Guide. Please contact Cirrus Logic at www.cirrus.com for additional information regarding security features.
Page 811: Chapter 30. Glossary
Inter-IC Sound, also known as I2S In-circuit Emulator Integrated Drive Electronics Ir or IR Infrared IrDA Infrared Data Association Standard Interrupt Request International Standards Organization JTAG Joint Test Action Group LCDDAC Liquid Crystal Display Digital to Analog Converter DS785UM1 30-1 Copyright 2007 Cirrus Logic...
Page 812 Thin Film Transistor Translation Lookaside Buffer Translation Table Base UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus Vectored Interrupt Controller Watchdog A count down timer designed to restart the ARM Core if the processor hangs. 30-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 813: Chapter 31. Ep93Xx Register List
22-20 AC97ISRx 22-14 AC97Reset 22-22 AC97RGIS 22-18 AC97RXCRx 22-7 AC97S12Data 22-17 AC97S1Data 22-15 AC97S2Data 22-16 AC97SRx 22-12 AC97SYNC 22-23 AC97TXCRx 22-10 ACRate 7-56 9-52 APBWait 5-22 BACKGROUND 8-35 BASEx 10-29 BCRx 10-41 BkgrndOffset 7-65 DS785UM1 31-1 Copyright 2007 Cirrus Logic...
Page 814 CONTROL 10-22 CONTROL 10-31 CURRENTx 10-30 CursorAdrReset 7-67 CursorAdrStart 7-66 CursorBlinkColor1, 7-69 CursorBlinkColor2 7-69 CursorBlinkRateCtrl 7-72 CursorColor1, 7-69 CursorColor2, 7-69 CursorDScanLHYLoc 7-71 CursorSize 7-68 CursorXYLoc 7-70 DAR_BASEx 10-43 DAR_CURRENTx 10-44 DESTLINELENGTH 8-29 DESTPIXELSTRT 8-23 31-2 DS785UM1 Copyright 2007 Cirrus Logic...
Page 815 9-62 GPIOxDB 28-14 GPIOxEOI 28-14 GPIOxIntEn 28-12 GPIOxIntType1 28-12 GPIOxIntType2 28-13 GrySclLUTG, 7-73 GrySclLUTR, 7-73 9-49 HActiveStrtStop 7-43 HashTbl 9-54 HBlankStrtStop 7-44 HcBulkCurrentED 11-23 HcBulkHeadED 11-22 HcCommandStatus 11-15 HcControl 11-12 HcControlCurrentED 11-22 HcControlHeadED 11-21 DS785UM1 31-3 Copyright 2007 Cirrus Logic...
Page 816 HSyncStrtStop 7-42 I2SClkDiv 5-31 I2SGlCtrl 21-31 I2SGlSts 21-29 I2SRX0En 21-24 I2SRX0Lft 21-19 I2SRX0Rt 21-20 I2SRX1En 21-24 I2SRX1Lft 21-20 I2SRX1Rt 21-21 I2SRX2En 21-25 I2SRX2Lft 21-21 I2SRX2Rt 21-22 I2SRXClkCfg 21-27 I2SRXCtrl 21-23 I2SRXLinCtrlData 21-22 I2SRXWrdLen 21-23 31-4 DS785UM1 Copyright 2007 Cirrus Logic...
Page 817 IDEMDMAOp 27-12 IDEUDMADataIn 27-16 IDEUDMADataOut 27-15 IDEUDMADebug 27-18 IDEUDMAOp 27-12 IDEUDMARdBufSts 27-19 IDEUDMASts 27-16 IDEUDMAWrBufSts 27-18 IndAd 9-53 IntEn 9-57 INTERRUPT 10-35 INTERRUPT 10-25 IntStsP/IntStsC 9-60 IntStsX 28-15 IrAdrMatchVal 17-25 IrCtrl 17-24 IrData 17-27 DS785UM1 31-5 Copyright 2007 Cirrus Logic...
Page 818 MIIR 17-34 MIISts 9-66 MIMR 17-33 MIRClkDiv 5-30 MISR 17-32 ParllIfIn 7-61 ParllIfOut 7-60 PattrnMask 7-65 PCAttribute 12-13 PCCommon 12-14 PCIO 12-15 PCMCIACtrl 12-17 PixelMode 7-57 PPALLOC 10-23 PWMxDutyCycle 24-4 PWMxEn 24-5 PWMxInvert 24-5 31-6 DS785UM1 Copyright 2007 Cirrus Logic...
Page 819 RXBCA 9-74 RXBufThrshld 9-85 RXCtl 9-41 RXDCurAdd 9-73 RXDEnq 9-74 RXDQBAdd 9-71 RXDQBLen 9-72 RXDQCurLen 9-72 RXDThrshld 9-89 RXHdrLen 9-78 RXMissCnt 9-55 RXRuntCnt 9-56 RXStsEnq 9-78 RXStsQBAdd 9-75 RXStsQBLen 9-76 RXStsQCurAdd 9-77 RXStsQCurLen 9-76 DS785UM1 31-7 Copyright 2007 Cirrus Logic...
Page 820 5-17 STATUS 10-26 STATUS 10-37 STFClr 5-18 SysCfg SysCfg 5-34 SysSWLock 5-35 TEOI 5-17 TestCtl 9-57 Timer1Clear, 18-5 Timer1Control, 18-6 Timer1Load, 18-3 Timer1Value, 18-4 Timer2Clear, 18-5 Timer2Control, 18-6 Timer2Load 18-3 Timer2Value 18-4 Timer3Clear 18-5 31-8 DS785UM1 Copyright 2007 Cirrus Logic...
Page 821 TXDEnq 9-82 TXDQBAdd 9-79 TXDQBLen 9-80 TXDQCurAdd 9-81 TXDQCurLen 9-80 TXDThrshld 9-90 TXStsQBAdd 9-82 TXStsQBLen 9-83 TXStsQCurAdd 9-84 TXStsQCurLen 9-84 TXStsThrshld 9-88 UART1Ctrl 14-22 UART1Data 14-17 UART1DMACtrl 14-25 UART1Flag 14-22 UART1HDLCAddMask 14-31 UART1HDLCAddMtchVal 14-30 DS785UM1 31-9 Copyright 2007 Cirrus Logic...
Page 822 UART2RXSts 15-8 UART2TMR 15-17 UART3Ctrl 16-8 UART3Data 16-3 UART3DMACtrl 16-11 UART3Flag 16-9 UART3HDLCAddMask 16-16 UART3HDLCAddMtchVal 16-16 UART3HDLCCtrl 16-13 UART3HDLCRXInfoBuf 16-17 UART3HDLCSts 16-18 UART3IntIDIntClr 16-10 UART3LinCtrlHigh 16-5 UART3LinCtrlLow 16-7 UART3LinCtrlMid 16-7 UART3LowPwrCntr 16-11 UART3ModemCtrl 16-12 31-10 DS785UM1 Copyright 2007 Cirrus Logic...
Page 823 VICxVectAddr0 6-15 VICxVectAddr1, 6-15 VICxVectAddr10, 6-16 VICxVectAddr11, 6-16 VICxVectAddr13, 6-16 VICxVectAddr14, 6-16 VICxVectAddr15 6-16 VICxVectAddr2, 6-15 VICxVectAddr3, 6-15 VICxVectAddr4, 6-15 VICxVectAddr5, 6-15 VICxVectAddr6 6-15 VICxVectAddr7, 6-16 VICxVectAddr8, 6-16 VICxVectCntl0, 6-17 VICxVectCntl1, 6-17 VICxVectCntl10, 6-17 DS785UM1 31-11 Copyright 2007 Cirrus Logic...
Page 824 VICxVectCntl5, 6-17 VICxVectCntl6, 6-17 VICxVectCntl7, 6-17 VICxVectCntl8, 6-17 VICxVectCntl9, 6-17 VidClkDiv 5-29 VideoAttribs 7-51 VidScrnHPage 7-46 VidScrnPage 7-46 VidSigCtrl 7-78 VidSigRsltVal 7-77 VLineStep 7-48 VLinesTotal 7-38 VSigStrtStop 7-79 VSyncStrtStop 7-38 Watchdog 19-3 WDStatus 19-5 31-12 DS785UM1 Copyright 2007 Cirrus Logic...
Page 825 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic EP9315-CBZ EP9315-IBZ...

This manual is also suitable for:

Ep9315 Ep9301 Ep9302 Ep9307 Ep9312

Cirrus Logic EP93 Series User Manual

Preface

About the Ep93Xx User's Guide

Related Documents from Cirrus Logic

Reference Documents

Notational Conventions

Register Example

Chapter 1. Introduction

Introduction

Ep93Xx Features

Ep93Xx Processor Applications

Ep93Xx Processor Highlights

Chapter 2. ARM920T Core and Advanced High-Speed Bus (AHB)

Introduction

Overview: ARM920T Core

AHB Decoder

Chapter 3. Maverickcrunch Co-Processor

Introduction

Programming Examples

DSPSC Register

ARM Co-Processor Instruction Format

Instruction Set for the Maverickcrunch Co-Processor

Chapter 4. Boot ROM

Introduction

Boot Options

Chapter 5. System Controller

Introduction

Registers

Chapter 6. Vectored Interrupt Controller

Chapter 7. Raster Engine with Analog/Lcd Integrated

Timing and Interface

Introduction

Features

Raster Engine Features Overview

Functional Details

Registers

Chapter 8 . Graphics Accelerator

Overview

Block Processing Modes

Line Draws

Memory Organization for Graphics Accelerator

Register Programming

Register Usage

Registers

Chapter 9 . 1/10/100 Mbps Ethernet LAN Controller

Introduction

Descriptor Processor

Registers

Quick Links

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Questions and answers

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Summary of Contents for Cirrus Logic EP93 Series