Cirrus Logic EP93 Series User Manual page 458

Universal Serial Bus Host Controller
EP93xx User's Guide
11
HcInterruptEnable
31 30
MIE OC
15 14
Address:
Default:
Definition:
Bit Descriptions:
11-18
FNO:
RHSC:
OC:
29 28 27 26
13 12 11 10
RSVD
0x8002_0010
0x0000_0000
Enables interrupt sources.
RSVD:
SO:
WDH:
SF:
RD:
UE:
Copyright 2007 Cirrus Logic
FrameNumberOverflow. This bit is set when the MSB of
HcFmNumber (bit 15) changes value, from 0 to 1 or from 1
to 0, and after HccaFrameNumber has been updated.
RootHubStatusChange. This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
OwnershipChange. This bit is set by HC when HCD sets
the OwnershipChangeRequest field in
HcCommandStatus. This event, when unmasked, will
always generate a System Management Interrupt (SMI)
immediately. This bit is tied to 0b when the SMI pin is not
implemented.
25 24 23 22
RSVD
9 8 7 6
RHSC
Reserved. Unknown During Read.
SchedulingOverrun. Enable interrupt generation due to
Scheduling Overrun.
WritebackDoneHead. Enable interrupt generation due to
HcDoneHead Writeback.
StartofFrame. Enable interrupt generation due to Start of
Frame.
ResumeDetected. Enable interrupt generation due to
Resume Detect.
UnrecoverableError. Enable interrupt generation due to
Unrecoverable Error.
21 20 19 18
5 4 3 2
FNO UE RD SF
17 16
1 0
WDH SO
DS785UM1