Setup And Hold Time Requirements On Sfrmin With Respect To Sclkin In Microwire Mode; Figure 23-10. Microwire Frame Format (Continuous Transfers); Figure 23-11. Microwire Frame Format, Sfrmin Input Setup And Hold Requirements - Cirrus Logic EP93 Series User Manual

Synchronous Serial Port
EP93xx User's Guide
SCLK
SFRM
SSPTXD
23
SSPRXD
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
Respect to SCLKIN in Microwire Mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge
of SCLKIN after SFRMIN has gone LOW. Masters that drive a free-running SCLKIN must
ensure that the SFRMIN signal has sufficient setup and hold margins with respect to the
rising edge of SCLKIN.
Figure 23-11
rising edge on which the first bit of receive data is to be sampled by the SSP slave, SFRMIN
must have a setup of at least two times the period of SCLKIN on which the SSP operates.
With respect to the SCLKIN rising edge previous to this edge, SFRMIN must have a hold of
at least one SCLKIN period.
23-12
LSB
0
MSB
4 to 16 bits output data

Figure 23-10. Microwire Frame Format (Continuous Transfers)

illustrates these setup and hold time requirements. With respect to the SCLKIN
S C L K IN
S F R M IN
S S P R X D
t
clkm ax

Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements

MSB
LSB
t = t
h o ld S S P C L K IN
0 M S B
F irst R X d ata b it to b e
sam p led b y S S P slave
Copyright 2007 Cirrus Logic
LSB
8-bit control
t = (2t )
setup S S P C L K IN
MSB
DS785UM1