Cirrus Logic EP93 Series User Manual page 151

DeviceCfg
31 30 29 28
SWRST D1onG D0onG IonU2
15 14 13 12
HC3IN HC3EN HC1IN HC1EN
Address:
0x8093_0080 - Read/Write, Software locked
Default:
0x0000_0000
Definition:
Device Configuration Register. This register controls the operation of major
system functions.
Bit Descriptions:
RSVD:
0:
SHena:
KEYS:
ADCPD:
RAS:
RasOnP3:
DS785UM1
27 26 25 24
GonK TonG MonG U3EN
11 10 9 8
HonIDE GonIDE PonG EonIDE
Reserved. Unknown During Read.
This bit must be written as "0".
Standby/Halt enable. When 1, allows the system to enter
Standby or Halt on a read from the Standby and Halt
registers, respectively.
Key matrix inactive.
1 - Key Matrix controller inactive,
0 - Key Matrix controller active.
ADC Power Down.
1 - ADC and clocks are powered down.
0 - ADC and clocks are active. ADCPD must be zero for
normal touch screen operation and for direct ADC
operation.
Raster inactive.
1 - Disables video pixel clock to most of the Raster engine,
0 - Normal video clock to Raster engine.
Raster On SDRAM Port 3.
1 - The Raster video refresh SDRAM accesses use the
system primary AHB to get video data.
0 - Raster video refresh uses the private AHB on SDRAM
Port 0.
Copyright 2007 Cirrus Logic
23 22 21 20
CPENA A2onG A1onG U2EN
7 6 5 4
I2Son I2Son 0 RASOn
SSP AC97 P3
System Controller
EP93xx User's Guide
19 18 17 16
EXVC U1EN TIN RSVD
3 2 1 0
RAS ADCPD KEYS SHena
5-25
5