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Preliminary Product Information
http://www.cirrus.com
CobraNet
S i l i c o n S e r i e s
CS18100, CS18101, CS18102,
Hardware User's Manual
Version 2.1
Replaces DS651UM20
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
©
Copyright 2004 Cirrus Logic, Inc.
Digital Audio Networking Processor
™
CM-2
and
CS181xx
Oct 2004
DS651UM21
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Summary of Contents for Cirrus Logic CobraNet Silicon Series
- Page 1 CM-2 Hardware User’s Manual Version 2.1 Replaces DS651UM20 This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. © Copyright 2004 Cirrus Logic, Inc. Oct 2004 DS651UM21 http://www.cirrus.com...
- Page 2 CobraNet Hardware User’s Manual 32-bit Audio Decoder DSP Family - NOTES - © Copyright 2004 Cirrus Logic, Inc. DS651UM21...
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Page 3: Table Of Contents
7.3.1.6. Packet Transmit ..................28 7.3.1.7. Goto Counters ..................28 7.3.2 Status ......................29 7.3.3 Data....................... 30 7.3.3.1. Region length ..................30 7.3.3.2. Writable Region ..................30 7.3.3.3. Translation Complete ................30 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 4: List Of Figures
Figure 26. CM-2 RevE Schematic Page 5 of 7 ..................46 Figure 27. CM-2 RevE Schematic Page 6 of 7 ..................47 Figure 28. CM-2 RevE Schematic Page 7 of 7 ..................48 Figure 29. 144-Pin LQFP Package Drawing ..................49 © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 5: Introduction
CobraNet system. Isochronous Data Isochronous Data (Audio) (Audio) Ethernet Ethernet Unregulated Unregulated Traffic Traffic Control Data Control Data Clock Clock Figure 1. CobraNet Data Services © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 6: Features
• LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status • Watchdog Timer Output for System Integrity Assurance • Comprehensive Power-on Self-test (POST) • Error and Fault Reporting and Logging Mechanisms © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 7: Host Interface
• Two levels of inward audio routing affords flexibility in audio I/O interface design in the host system. • Local Audio Loopback and Output Duplication Capability • Peak-read Audio Metering with Ballistics © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 8: Hardware
CS181xx. The VCXO frequency is carefully adjusted to achieve lock with the network clock. The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast Ethernet standard. As per Ethernet requirements the interface is transformer isolated. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 9: Pinout And Signal Descriptions
"Synchronous Serial (Audio) Signals" on page 13 • "Audio Clock Signals" on page 13 • "Miscellaneous Signals" on page 14 • "Power and Ground Signals" on page 14 • "System Signals" on page 15 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 10: Cs181Xx Package Pinouts
ADDR6 VDDD DAI1_DATA1 GPIO0 DAI1_DATA0 ADDR5 GPIO1 VDDIO DATA7 DAI1_SCLK DATA6 VDDD HACK DAI1_LRCLK DATA5 ADDR4 DATA4 ADDR3 HREQ VDDIO HADDR3 DATA3 ADDR2 HADDR2 DATA2 ADDR1 HR/W IRQ1 ADDR0 GPIO2 IRQ2 © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 11: Connector Pinout
J3/J4 J1/J2 J3/J4 DAO1_DATA1 J3/J4 J1/J2 VCC_+3.3V J3/J4 DAO1_DATA2 J3/J4 VCC_+5V J1/J2 J3/J4 DAO1_DATA3 J3/J4 VCC_+5V J1/J2 VCC_+3.3V J3/J4 DAI1_DATA0 J3/J4 AUX_POWER3 J1/J2 J3/J4 DAI1_DATA1 J3/J4 AUX_POWER1 J1/J2 VCC_+3.3V J3/J4 DAI1_DATA2 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 12: Signal Descriptions
Asynchronous Serial UART_RXD J1:A1 Pull-up to VCC if unused. Receive Data Asynchronous Serial UART_TXD J1:B1 Transmit Data Enable transmit (active high) drive for two UART_TX_OE Transmit Drive Enable J1:A2 wire multi-drop interface. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 13: Synchronous Serial (Audio) Signals
Master audio MCLK_OUT J3:A4 Low jitter 24.576 MHz master audio clock. clock output *An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out implementation. © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 14: Miscellaneous Signals
13, 21, 27, 36, 47, B4, B2 57, 63, 69, 76, 86, Digital Ground 94, 101, 116, 122, J3:B16, B15, B13, 126, 133, 139 B11, B9, B7, B5, B3, B1 Indicates specifications are estimates. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 15: System Signals
Reference Clock Input / Crystal Oscillator Input Crystal Oscillator Output XTAL_OUT A Buffered Version of XTI FILT2, FILT1 PLL Loop Filter 127, 128 DAO_MCLK MCLK Input HS[3:0] CS181xx Boot Mode Selection 11, 16, 17, 19 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 16: Synchronization
However, it is not reasonable to assume that by setting a high conductor priority, you will always assume the conductor role. For more information, refer to CobraNet Programmer’s Reference Manual. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 17: Internal Mode
The external clock source must be synchronous with the network conductor. This mode is useful in installations where a house sync source is readily available. © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 18: External Master Clock Mode
Conductor—The entire network is synchronized to the supplied master clock. Performer—The node will initially lock to the network clock and will “jam sync” via the supplied master clock. The external clock source must be synchronous with the network conductor. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 19: Digital Audio Interface
DSP for synchronous outputs. Bit 31 is always the most significant (sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits 15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic recommends driving unused LS bits to zero. -
Page 20: Digital Audio Interface Timing
Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the edge of DAO1_SCLK. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 21: Normal Mode Data Timing
24-bit audio data. The MSB is left justified and arrives one bit period following FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge. © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 22: Standard Mode Data Timing
24-bit audio data. The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 23: Host Management Interface (Hmi)
HACK may be wired to an interrupt request input on the host. HACK can be made to assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see “Messages” below). © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... - Page 24 NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ# pin/bit should be observed to prevent overflowing the input data buffer. © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1...
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Page 25: Figure 14. Host Port Read Cycle Timing
H R /W m rw su m w d m w trd H D S m rw irq l H R E Q Figure 15. Host Port Write Cycle Timing © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 26: Protocol And Messages
0xB5 Buffer Goto Translation write 0xB5 Acknowledge Packet 0xB5 Receipt Transmit Packet 0xB5 Goto Counters read 0xB5 Goto Packet Receive read 0xB5 Buffer Goto Translation read 0xB5 Table 4. HMI messages © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 27: Translate Address
= 0 ) int msgack = MSG_D; MSG_C = write ? MOP_GOTO_TRANSLATION_WRITE : MOP_GOTO_TRANSLATION_READ; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 28: Packet Received
Moves HMI data pointers to interrupt status variables (beginning at hackStatus). void GotoCounters( void ) int msgack = MSG_D; MSG_C = MOP_GOTO_COUNTERS; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 29: Status
"HMI Access Code" on page Status Bit(s) Reserved [31:24] Region Length [23:8] Reserved [7:5] Writable Region Translation Complete Packet Transmission Complete Received Packet Available Message Togglebit Table 5. HMI status bits © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 30: Data
= MSG_D; /* record current state of togglebit */ MSG_D = YOUR_COMMAND_HERE; /* issue command */ /* wait for togglebit to flip */ while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 31: Hmi Reference Code
/*======================================================================== ** hmi.h ** CobraNet Host Management Interface example code ** Definitions **------------------------------------------------------------------------ ** $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. **========================================================================*/ #define MSG_A 0 #define MSG_B 1 #define MSG_C 2 #define MSG_D 3... -
Page 32: Hmi Access Code
** hmi.c ** CobraNet Host Management Interface example code ** Simple edition **------------------------------------------------------------------------ ** $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. **========================================================================*/ #include "hmi.h" /* variables model HMI state */ long PeekLimit; long PeekPointer = -1;... - Page 33 WriteRegister( DATA_C, (unsigned char) ( ( value >> 8 ) & 0xff ) ); WriteRegister( DATA_D, (unsigned char) ( value & 0xff ) ); /* maintain local pointers */ PokePointer++; PeekPointer = -1; /* force SetAddress()next Peek() to freshen data */ © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1...
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Page 34: Auto-Detection
DATA_C == ( 18101 >> 8 ) ) if( DATA_D == ( 18101&0xff ) { return 2; /* CM-2 detected */ return 0; /* no interface or non-supported interface */ © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 35: Mechanical Drawings And Schematics
"CM-2 RevE Schematic Page 5 of 7" on page 46 • "CM-2 RevE Schematic Page 6 of 7" on page 47 • "CM-2 RevE Schematic Page 7 of 7" on page 48 • "144-Pin LQFP Package Drawing" on page 49 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 36: Mechanical Drawings
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics CM-2 Mechanical Drawings DM9000 Flash DM9000 CS181xx Figure 16. CM-2 Module Assembly Drawing © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 37: Figure 17. General Pcb Dimensions
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 17. General PCB Dimensions © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 38: Figure 18. Example Configuration, Side View
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 18. Example Configuration, Side View © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 39: Figure 19. Faceplate Dimensions
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 19. Faceplate Dimensions © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 40: Figure 20. Case Cutout For Faceplate Mounting
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Required Panel Cutout Figure 20. Case Cutout for Faceplate Mounting © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 41: Figure 21. Connector Detail
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Component Side Up Figure 21. Connector Detail © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 42: Schematics
A linear regulator would dissapate about 0.75 watts max, This switching regulator dissapates about 0.10 watts max. Figure 22. CM-2 RevE Schematic Page 1 of 7 © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 43: Figure 23. Cm-2 Reve Schematic Page 2 Of 7
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics LED_BUF[0..7] Figure 23. CM-2 RevE Schematic Page 2 of 7 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 44: Figure 24. Cm-2 Reve Schematic Page 3 Of 7
DATA1 ADDR5 DATA0 ADDR4 ADDR3 BYTE# ADDR2 NC/VPP VCC_+3.3 ADDR1 NC/WP# VCC_+3.3 NC/RY/BY# HRESET_BUF# HRESET_BUF# RESET# FLASH_CS# FLASH_CS# FLASH_TSOP VCC_+3.3 0.1 uF Figure 24. CM-2 RevE Schematic Page 3 of 7 © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 45: Figure 25. Cm-2 Reve Schematic Page 4 Of 7
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 25. CM-2 RevE Schematic Page 4 of 7 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 46: Figure 26. Cm-2 Reve Schematic Page 5 Of 7
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 26. CM-2 RevE Schematic Page 5 of 7 © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 47: Figure 27. Cm-2 Reve Schematic Page 6 Of 7
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 27. CM-2 RevE Schematic Page 6 of 7 © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 48: Figure 28. Cm-2 Reve Schematic Page 7 Of 7
CobraNet Hardware User’s Manual Mechanical Drawings and Schematics Figure 28. CM-2 RevE Schematic Page 7 of 7 © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... -
Page 49: Cs181Xx Package
22.00 BSC .866” 20.00 BSC .787” 0.50 BSC .020” θ 0° 7° 0° 7° 0.45 0.60 0.75 .018” .024” .030” 1.00 REF .039” REF TOLERANCES OF FORM AND POSITION 0.08 .003” © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1... -
Page 50: Temperature Specifications
Mechanical Drawings and Schematics Temperature Specifications θ ° • Thermal Coefficient (junction-to-ambient): - 38 C / Watt • Ambient Temperature Range: 0-70 deg C • Junction Temperature Range: 0-125 deg C © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1... - Page 51 CobraNet Hardware User’s Manual Mechanical Drawings and Schematics © DS651UM21 Copyright 2004 Cirrus Logic, Inc. Version 2.1...
- Page 52 C P atent R ights to use those com ponents in a standard C system . C O P Y R IG H T © 2004 C IR R U S LO G IC , IN C . © Copyright 2004 Cirrus Logic, Inc. DS651UM21 Version 2.1...
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