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Cirrus Logic CS485 Series Manuals
Manuals and User Guides for Cirrus Logic CS485 Series. We have
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Cirrus Logic CS485 Series manual available for free PDF download: User Manual
Cirrus Logic CS485 Series User Manual (102 pages)
32-bit Audio DSP Family
Brand:
Cirrus Logic
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
3
Contents
4
Figures
5
Chapter 1. Introduction
9
Overview
9
Chip Features
9
Figure 1-1. CS48560 Chip Functional Block Diagram
10
Figure 1-2. CS48540 Chip Functional Block Diagram
11
Figure 1-3. CS48520 Chip Functional Block Diagram
12
Code Overlays
13
Functional Overview of the Cs485Xx Chip
14
Debug Controller (DBC)
14
Digital Audio Output (DAO) Controller
14
DSP Core
14
Digital Audio Input (DAI) Controller
15
Direct Stream Digital (DSD) Controller
15
General Purpose I/O
15
Serial Control Ports (SPI or I Standards)
15
Clock Manager and PLL
16
DMA Controller
16
Internal Timers
16
Serial Flash Controller
16
Watchdog Timer
16
Programmable Interrupt Controller
17
Chapter 2. Operational Modes
19
Introduction
19
Figure 2-1. Operation Mode Block Diagrams
19
Operational Mode Selection
20
Slave Boot Procedures
20
Table 2-1. Operation Modes
20
Performing a Slave Boot
21
Figure 2-2. Slave Boot Sequence
22
Slave Boot Procedure
23
Boot Messages
24
Messages Read from Cs485Xx
24
Slave Boot
24
Soft Reset
24
Table 2-2. SLAVE_BOOT Message for Cs485Xx
24
Table 2-3. SOFT_RESET Message for Cs485Xx
24
Table 2-4. Boot Read Messages from Cs485Xx
24
Slave Boot
21
Figure 2-3. Master Boot Sequence Flowchart
25
Master Boot Procedure
25
Table 2-5. Boot Command Messages for Cs485Xx
25
Softboot
26
Softboot Messaging
26
Softboot Procedure
26
Table 2-6. SOFTBOOT Message
26
Figure 2-4. Soft Boot Sequence Flowchart
27
Softboot Example
27
Softboot Steps
27
Figure 2-5. Soft Boot Example Flowchart
28
Low Power Mode
30
Getting into Low Power Mode
30
Getting out of Low Power Mode
30
Low Power Mode Messaging
30
Figure 2-6. Flowchart of Steps Used to Exit Low Power Mode
31
Table 2-8. Wakeup_Uld Options and Values
32
Chapter 3. Serial Control Port
33
Introduction
33
Serial Control Port Configuration
33
I 2 C Port
34
Figure 3-1. Serial Control Port Internal Block Diagram
34
I 2 C System Bus Description
35
Figure 3-3. I 2 C Start and Stop Conditions
36
I 2 C Bus Dynamics
36
Table 3-1. Serial Control Port 1 I2C Signals
36
Figure 3-4. I 2 C Address with ACK and NACK
37
Figure 3-5. Data Byte with ACK and NACK
38
Figure 3-6. Stop Condition with ACK and NACK
38
Figure 3-7. Repeated Start Condition with ACK and NACK
39
I 2 C Messaging
39
Performing a Serial I C Write
39
Figure 3-8. I 2 C Write Flow Diagram
40
Performing a Serial I C Read
41
Figure 3-9. I 2 C Read Flow Diagram
42
SPI Port
45
Figure 3-12. SPI Serial Control Port Internal Block Diagram
45
SPI System Bus Description
46
Table 3-2. Serial Control Port SPI Signals
46
Figure 3-13. Block Diagram of SPI System Bus
47
SPI Bus Dynamics
47
Figure 3-14. SPI Address and Data Bytes
48
Performing a Serial SPI Write
49
SPI Messaging
49
Figure 3-15. SPI Write Flow Diagram
50
Performing a Serial SPI Read
50
Figure 3-16. SPI Read Flow Diagram
51
Figure 3-17. Sample Waveform for SPI Write Functional Timing
53
Figure 3-18. Sample Waveform for SPI Read Functional Timing
53
Chapter 4. Digital Audio Input Interface
55
Introduction
55
Digital Audio Input Port Description
55
DAI Pin Description
56
Table 4-1. Digital Audio Input Port
56
Supported DAI Functional Blocks
57
Dual Clock Domain - 10 Channel Input
57
Figure 4-1. 10-Channel DAI Port Block Diagram
57
Figure 4-2. 8-Channel DAI Port Block Diagram
57
Figure 4-3. 6-Channel DAI Port Block Diagram
58
Single Clock Domain - 12 Channel Input
58
Digital Audio Formats
59
Figure 4-4. 12-Channel DAI Port Block Diagram
59
I 2 S Format
59
Left-Justified Format
60
DAI Hardware Configuration
60
DAI Hardware Naming Convention
60
Figure 4-5. I 2 S Format (Rising Edge Valid SCLK)
60
Figure 4-6. Left-Justified Format (Rising Edge Valid SCLK)
60
Table 4-2. Input Data Format Configuration (Input Parameter A)
61
Table 4-3. Input SCLK Polarity Configuration (Input Parameter B)
62
Table 4-4. Input LRCLK Polarity Configuration (Input Parameter C)
62
Table 4-5. DAI2_DATA Clock Source (Input Parameter E)
63
Table 4-6. DAI1_DATA Clock Source (Input Parameter F)
63
Table 4-7. Chip Version (Input Parameter G)
63
Table 4-8. DAII TDM (Input Parameter H)
63
Chapter 5 . Direct Stream Data (DSD) Input Interface
65
Digital Audio Input Port Description
65
DSD Pin Description
65
Supported DSD Functional Blocks
65
Table 5-1. Dsdl Audio Input Port
65
Figure 5-1. DSD Port Block Diagram on CS48560
66
Chapter 6. Digital Audio Output Interface
67
Introduction
67
Digital Audio Output Port Description
67
DAO Pin Description
67
Table 6-1. Digital Audio Output (DAO) Pins
67
Figure 6-1. CS48560 DAO Block Diagram
68
Figure 6-2. CS48540 DAO Block Diagram
69
Figure 6-3. CS48520 DAO Block Diagram
69
Supported DAO Functional Blocks
70
DAO Interface Formats
70
I 2 S Format
70
Left-Justified Format
70
DAO Hardware Configuration
71
Figure 6-6. One-Line Data Mode Digital Audio Formats
71
One-Line Data Mode Format (Multichannel)
71
Table 6-2. Output Clock Mode Configuration (Parameter A)
71
Table 6-3. DAO1 & DAO2 Clocking Relationship Configuration (Parameter B)
72
Table 6-4. Output DAO_SCLK/LRCLK Configuration (Parameter C)
72
Table 6-5. Output Data Format Configuration (Parameter D)
74
S/PDIF Transmitter
75
Table 6-6. Output DAO_LRCLK Polarity Configuration (Parameter E)
75
Table 6-7. Output DAO_SCLK Polarity Configuration (Parameter F)
75
Table 6-8. DAO TDM (Parameter G)
75
Table 6-10. S/PDIF Transmitter Configuration
76
Table 6-9. S/PDIF Transmitter Pins
76
Chapter 8 . General Purpose Input/Output Pins
79
Introduction
79
GPIO Description
79
Watchdog Timer Description
80
Typical Connection Diagrams
81
Pin Description
90
Power and Ground
90
Power
90
Copyright 2009 Cirrus Logic
90
Ground
91
Decoupling
91
PLL Filter
91
Analog Power Conditioning
91
Clocking
92
Control
92
Pll
92
Operational Mode
93
48-Pin LQFP Pin Assigments
94
Pin Assignments
97
Revision History
101
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