Registers - Cirrus Logic EP93 Series User Manual

15.4 Registers

Register Descriptions
UART2Data
31 30 29 28
15 14 13 12
Address:
0x808D_0000 - Read/Write
Default:
0x0000_0000
Definition:
UART Data Register
Bit Descriptions:
RSVD:
DATA:
DS785UM1
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
UART Data, read for receive data, write for transmit data
For words to be transmitted:
• if the FIFOs are enabled, data written to this location is
pushed onto the transmit FIFO
• if the FIFOs are not enabled, data is stored in the
transmitter holding register (the bottom word of the
transmit FIFO). The write operation initiates transmission
from the UART. The data is prefixed with a start bit,
appended with the appropriate parity bit (if parity is
enabled), and a stop bit. The resultant word is then
transmitted.
For received words:
• if the FIFOs are enabled, the data byte is extracted, and
a 3-bit status (break, frame and parity) is pushed onto the
11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are
stored in the receiving holding register (the bottom word of
the receive FIFO).
Copyright 2007 Cirrus Logic
24 23 22 21
RSVD
8 7 6 5
UART2
EP93xx User's Guide
20 19 18 17
4 3 2 1
DATA
15
16
0
15-7