Table 5-2. Boot Configuration Options - Cirrus Logic EP93 Series User Manual

The normal boot function is described in
Serial boot is functionally identical to normal boot except that the SBoot bit in the SysCfg
register is set. This mode is available for a software configuration option that is readable by
the boot code.
In either normal boot or serial boot mode, once the processor starts up, it will begin to
execute the instruction at logical address 0x0000_0000. Various configuration options are
provided to select a memory device for booting from at address location 0. The options are
listed in Table 5-2.
EECLK EEDAT BOOT1
0 1
0 1
1 1
1 1
1 1
1 1
DS785UM1
Chapter 4 on page

Table 5-2. Boot Configuration Options

BOOT0 ASDO CSn[7:6]
0 0 1
0 0 0
0 1 x
0 0 x
0 0 1
0 0 0
Copyright 2007 Cirrus Logic
4-1.
Boot Configuration
External boot fusing Sync boot mode and SDCSn3.
The media type must be either SROM or SyncFLASH.
The selection of the bus width is determined by latched
CSn[7:6] value:
0 0 16-bit
0 1 16-bit
1 0 32-bit
1 1 32-bit
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6] value:
8-bit
0 0
16-bit
0 1
32-bit
1 0
32-bit
1 1
xx Internal boot from UART1.
xx Internal SPI boot if HeaderID is found.
Internal boot using Sync boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
16-bit
16-bit
0 0
32-bit
0 1
32-bit
1 0
See memory map in Table 2-7 on page 2-16
1 1
boot mode.
Internal boot using Async boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
8-bit
16-bit
0 0
32-bit
0 1
32-bit
1 0
See memory map in Table 2-7 on page 2-16
1 1
ASYNC boot mode.
System Controller
EP93xx User's Guide
for SYNC
for
5-3
5