Cirrus Logic EP93 Series User Manual page 390

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
9
TXStsThrshld
31 30
15 14
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
9-88
29 28 27 26
RSVD
13 12 11 10
RSVD
0x8001_00DC - Read/Write
0x0004_0002
0x0000_0000
Unchanged
Transmit Status Threshold register. The transmit status thresholds are used to
set a limit on the amount of transmit status which is held in the transmit status
FIFO before a bus request will be scheduled. When the number of words in
the FIFO exceeds the threshold value, the Descriptor Processor will schedule
a bus request to transfer status. The lower two bits of the thresholds are
always zero.
RSVD:
0:
TSHT:
TSST:
Copyright 2007 Cirrus Logic
The hard and soft threshold work in exactly the same
manner except one. The soft threshold will not cause a
bus request to be made if the bus is currently in use, but
only when it is deemed to be idle (no transfers for four
AHB clocks). The hard threshold takes effect immediately
regardless of the state of the bus. This operation allows for
more efficient use of the AHB bus by allowing smaller
transfers to take place when the bus is lightly loaded and
requesting larger transfers only when the bus is more
heavily loaded.
25 24 23 22
9 8 7 6
Reserved. Unknown During Read.
Must be written as "0".
Transmit Status Hard Threshold.
Transmit Status Soft Threshold.
21 20 19 18
TSHT
5 4 3 2
TSST
17 16
0 0
1 0
0 0
DS785UM1