Cirrus Logic EP93 Series User Manual page 672

2
I S Controller
EP93xx User's Guide
I2STXLinCtrlData
31 30
15 14
21
Address:
Default:
Definition:
Bit Descriptions:
I2STXCtrl
31 30
15 14
Address:
Default:
21-16
29 28 27 26 25
13 12 11 10 9
RSVD
0x8082_0028 - Read/Write
0x0000_0000
Line Control Data Register
RSVD:
Left_Right_Justify: Determines how the data word is justified when being
TXUF_REPEAT_SAMPLE:On TX underflow, the I
TXDIR:
29 28 27 26
13 12 11 10
0x8082_002C - Read/Write
0x0000_0000
24 23 22 21 20
RSVD
8 7 6 5 4
Reserved. Unknown During Read.
transmitted on the sdo line output.
0 - left justified.
1 - right justified
zeros if this bit is "1".
If this bit is "0" the I
underflow.
Transmit data shift direction.
0 - MSB first
1 - LSB first
25 24 23 22
RSVD
9 8 7 6
RSVD
Copyright 2007 Cirrus Logic
19 18
3 2
Left_Right_Justify TXUF_REPEAT_SAMPLE
2
S controller transmits all
2
S controller repeats the last sample on
21 20 19 18
5 4 3 2
TXUFIE
17 16
1 0
TXDIR
17 16
1 0
TXEMPTY_int_level
DS785UM1