Table 2-6. Cp15 Arm920T Register Description - Cirrus Logic EP93 Series User Manual

• spsr: Saved Program Status Register contains CPSR after occurrence of an exception
CP15 has 16 registers that control the core as described in
DS785UM1

Table 2-6. CP15 ARM920T Register Description

Register
ID Code: (Read/Only) This register returns a 32-bit device ID code. ID Code data includes
the core type, revision, part number etc. Access to this register is via the instruction
MRC p15 0, Rd, c0, c0, 0.
0
Cache Code: This register will return cache type, size and length of both I-Cache and D-
Cache, and associativity. Access to this register is via the instruction
MRC p15 0, Rd, c0, c0, 1.
Control Register: (Read/Write) This register is used to enable: MMU, instruction and data
cache, round robin replacement 'RR'-bit, system protection, ROM protection, and clocking
1
mode. Read/Write Instructions are:
MRC p15, 0, Rd, c1, c0, 0 - Read control register - value stored in Rd
MCR p15, 0, Rd, c1, c0, 0 - Write control register - value first loaded into Rd
Translation Base Table: (Read/Write) This register contains the start address of the first
level translation table. The upper 18 bits represent the pointer to the table base. The lower
2
14 bits should be all zeroes for a write, unpredictable if read.
MRC p15, 0, Rd, c2, c0, 0 - Read TTB
MCR p15, 0, Rd, c2, c0, 0 - Write TTB
Domain Access Control: (Read/Write) This register specifies permissions for each of the
16 domains. Read/Write Instructions are:
3
MRC p15, 0, Rd, c3, c0, 0
MCR p15, 0, Rd, c3, c0, 0
4
Reserved: Do not access. Unpredictable behavior may result.
Fault Status: (Read/Write) This register indicates the type of fault and the domain of the
most recent data abort. Read/Write Instructions are:
5
MRC p15, 0, Rd, c5, c0, 0 - read data FSR value
MCR p15, 0, Rd, c5, c0, 0 - write data FSR value
Fault Address: (Read/Write) This register contains the address of the last data access
abort. Read/Write Instructions are:
6
MRC p15, 0, Rd, c6, c0, 0 - read FAR data
MCR p15, 0, Rd, c6, c0, 0 - write FAR data
Cache Operation: (Write/Only) This register configures, or performs a clean (flush) of, the
cache and write buffer when written to. Example:
7
MRC p15, 0, Rd, c7, c7, 0 - Invalidate I/D-cache
MRC p15, 0, Rd, c7, c5, 0 - Invalidate I-Cache
TLB Operation: (Write/Only) This register configures, or performs a clean (flush) of, the
8 TLB when written to. Example:
MRC p15, 0, Rd, c8, c7, 0 - Invalidate TLB
Cache Lockdown: (Read/Write) This register prevents certain existing cache-lines from
being overwritten (locked) during a new cache-line fill. Examples:
9
MRC p15, 0, Rd, c9, c0, 1- Write lockdown base pointer for D-Cache
MRC p15, 0, Rd, c9, c0, 1 - Write lockdown base pointer for I-Cache
TLB Lockdown: (Read/Write) This register prevents existing TLB entries from being
erased during a table walk. Examples:
10
MRC p15, 0, Rd, c10, c0, 1- Write lockdown base pointer for data TLB entry
MRC p15, 0, Rd, c10, c0, 1 - Write lockdown base pointer for instruction TLB entry
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
Table 2-6.
Description
EP93xx User's Guide
2-15
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